Sir,
I have designed and a PCIe endpoint IP core using VHDL (X1,2.5/5 Gbps). At present the low power states are not developed and Xilinx Virtex6's GTX is used as the PHY.Functional validation of the core is done by integrating my core with Xilinx root complex available from Xilinx ISE13.1 with Questasim. Using Questssim the physical link initalization, speed negotiation, datalink layer initialization and configuration TLP exchanges are monitored.
Then I plugged Xilinx ML605 board with Virtex 6 FPGA on the motherboard of a PC and implemented PCIE endpoint core in it. when I restart the PC, I can see the working of LTSSM, exchange of DLLPs, configuration TLP transfers between the board and the PC through Chipscope analyzer. But most of the time my PC is not booting when PCIE core is available on its PCIe slot, BUT sometimes it is booting and showing 'device initialization error in PCIe slot'. So I doubt some error in the register settings of configuration space.
My intention is to monitor the configuration register space and transfer of some memory read/write request to the endpoint through 'PCI tree'.
For that I would like to know
1. What BIOS will do during PCIe bus enumeration? In which order BIOS access configuration registes? It is found that BIOS is repeatedly reading few registers.
2. Can I work without Low power support in the LTSSM
3. Can I work only with MSI (without INTx)
4. Can we set our own vendor ID (for checking)
5. Is their any standard method for testing PCIe endpoint.I do not have a protocol analyzer
6. Which are the mandatory registers in the Type0 Configuration space.
Will you please provide some relevant information about PCIE endpoint testing and debugging especially regarding configuration space, power management and interrupt mechanisms.
Regards
Jaya S
Senior Engineer
CDAC
Trivandrum,
India.