Eli,
According to the following paper, pcie is a little endian. In your blog it's big endian. Could you please clarify it?
http://www.intel.com/design/intarch/papers/endian.pdf
Thanks
eli wrote: byte zero in the DWord, which is related to bits [31:24] in the data packet.
// memory read NOTE: Little endian host assumed
4'b0111:
begin
tx_data[15:8] <= ReadData[7:0];
tx_data[7:0] <= ReadData[15:8];
State <= 4'b1000;
DataLength <= DataLength - 1;
end