BARs in type1 header

Comments and questions related to the "Down to the TLP" pages

BARs in type1 header

Postby Guest »

Hi ,
PCI/PCIE Config space Type 1 header has 2 BARs in it. Whenever a Downstream routed packet is received on the primary link of Switch Upstream port, it checks if the packet is intended for the US port itself(Checking against 2 BARs of T1 header) or secondary Link ports( Checking against the Base/Limit Registers).

I can't figure out when any SW US port will be targeted with a Memory Read/Write packet? Does a SW US port contain the memory(I dont think so)?


Regards,
Vismay
Guest
 

Re: BARs in type1 header

Postby support »

I have to admit that I haven't played around with switches. And indeed, running a plain lspci on my Linux machine reveals that the switches don't have any memory region allocated for themselves.

But at least theoretically, I could imagine that some switch vendor would like to set up a region for memory access. Suppose, for example, that the switch was used for sniffing TLP packets. In that case, the switch would also need to have its own registers and memory space. Well, it would make more sense to put the sniffer as an on-chip device hooked up on the switch, but I guess those who wrote the standard wanted to keep all options open.

And well, sometimes it's not so clear why certain features in a standard are there.
support
 
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Re: BARs in type1 header

Postby Guest »

Thanks Eli for your reply. I will search around for further details. I will post here if I find any more information.

Thanks and Regards,
Vismay.
Guest
 

Re: BARs in type1 header

Postby Guest »

Hello,

there are many reasons for a bridge to having its own memory/io resources (e.g. mail-registers for communication between multiple components). By IDT are complete manuals available for its PCIe-Bridges that has dedicated memory for its own use.
In my opinion (after reading the Bridge-Spec) the memory-range allocated to the BARs (for internal use) must be different from the memory-range allocated to the base/limit-registers (for routing to the secondary bus), this means the bridge has multiple resources (with different address-ranges) present on the primary bus.

Sorry, i do not have a part of text from the specification that can prove this view, but this is my personal understanding of the specification.

Regards,
Erik
Guest
 


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