P2N and P2P

Comments and questions to the author of the "Down to the TLP" posts (Eli Billauer)

P2N and P2P

Postby Guest » Sun Dec 16, 2012 5:29 pm

Hi,

First of all apologies - I am a novice wrt PCIe. So please excuse if this is a very trivial question.

I am trying to use a Cavium CN6020 device as a RC. It is connected to a Xilinx device. The BAR addresses are as below.
BAR0: 8000_0000h
BAR1: 8100_0000h
BAR2: 8200_0000h

I am confused about the P2N and P2P BAR registers that have been mentioned in the manual. Should I use P2P or P2N?
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Re: P2N and P2P

Postby support » Sun Dec 16, 2012 8:36 pm

In which manual did it say something about P2P or P2N?
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Re: P2N and P2P

Postby Guest » Mon Dec 17, 2012 5:36 am

Thanks for the reply. The Hardware reference manual (Cavium 6020 processor) has 6 possibilities ; BAR0, BAR1 and BAR2 as P2P (peer to peer) and BAR0, BAR1 and BAR2 as P2N (not sure what is N!). There is no good further explanation for the same.
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Re: P2N and P2P

Postby support » Mon Dec 17, 2012 10:59 am

It sounds like the BARs mentioned in the processor's manual are relevant when the processor behaves as an endpoint on the bus ("Gadget mode").

When the processor functions as a Root Complex, it enumerates other endpoints according to their BARs. It's own PCIe configuration space is irrelevant in this respect, since noone's asking for that information.

So I don't think there is anything to set up regarding the processor's BARs. Just make sure that the processor is set up to be a Root Complex.
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