The Xillybus Forum

Hi,

First of all apologies - I am a novice wrt PCIe. So please excuse if this is a very trivial question.

I am trying to use a Cavium CN6020 device as a RC. It is connected to a Xilinx device. The BAR addresses are as below.
BAR0: 8000_0000h
BAR1: 8100_0000h
BAR2: 8200_0000h

I am confused about the P2N and P2P BAR registers that have been mentioned in the manual. Should I use P2P or P2N?

In which manual did it say something about P2P or P2N?

Thanks for the reply. The Hardware reference manual (Cavium 6020 processor) has 6 possibilities ; BAR0, BAR1 and BAR2 as P2P (peer to peer) and BAR0, BAR1 and BAR2 as P2N (not sure what is N!). There is no good further explanation for the same.

It sounds like the BARs mentioned in the processor's manual are relevant when the processor behaves as an endpoint on the bus ("Gadget mode").

When the processor functions as a Root Complex, it enumerates other endpoints according to their BARs. It's own PCIe configuration space is irrelevant in this respect, since noone's asking for that information.

So I don't think there is anything to set up regarding the processor's BARs. Just make sure that the processor is set up to be a Root Complex.