Hi!
My IP core for 7series fpga is configured for an endpoint.I am trying to simulate DMA operations from the endpoint to the rootport using the RootPort Model Testbench from Xilinx(with the PIO design). However, the MEMWR request is not passed on to the rootport(dsport) and on a detailed look, cfg_dev_status_fatal_error_detected is set at the PCIe core of the rootport side. I have checked my tlp for payload size(128DW) and the header looks okay to me. My only doubt is the requester id. I have configured it with the requester id 0x0100 (as seen from lspci).
Also on loading the design on fpga, i see no data on the associated memory. There could also be a possibilty that the address is out of range for the rootport. How can one check that?
Thanks a ton!
Sati