Big gap between FIFO writes

[Guest]

Hello,

Board: VC707
Host OS: WIN10
Host CPU: i7 7700k

I'm running the "xillydemo" design on my VC707 board, and I modified the "streamwrite.c" so that it can read a input.txt file and write the contents to FPGA through xillybus_write_32 devfile.

My question is, why the FIFO signals captured by debug probes indicate that there are big gaps between the FIFO writes?
As shown in picture, the first write appears at cycle 512, while the second appears at cycle 2907.


Is this host program's problem or FPGA logic's problem?

Thanks a lot.

[support]

Hello,

To begin with, there is no guarantee on the exact behavior of the FIFO's wren signal. Gaps are expected, as the Xillybus IP core may tend to other business from time to time. Or just as a result of the PCIe overhead, if there's nothing else taking up bandwidth.

What you seem to be experiencing is a low bandwidth throughput. streamwrite wasn't written to efficient (it has a small buffer) and it may also be that the file I/O is slow.

I suggest trying the same with the "dd" or "cat" command line utilities. Note that there are Windows versions for these in the Xillybus' Windows package.

You may find this useful:

http://xillybus.com/doc/bandwidth-guidelines

Regards,
Eli