FPGA gives a "unknown header type 7f" with lspci command

Questions and discussions about the Xillybus IP core and drivers

FPGA gives a "unknown header type 7f" with lspci command

Postby Guest » Fri Oct 12, 2012 2:40 pm

Hi! I find your blog extremely useful and was hoping you could help out here!
I have a KC705 board with PCIe interface. I want to communicate with the fpga from the host PC by flashing it. I have generated an IP Core for PCIe as an endpoint device. I implemented the sample design and generated a bit file but once loaded on the fpga, it doesn't recognize my fpga. What could be wrong? Do you have an idea about it?

Would be great if you could help!
Soumya
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Re: FPGA gives a "unknown header type 7f" with lspci command

Postby support » Fri Oct 12, 2012 2:47 pm

Hello,

It's somewhat difficult to answer that, since your description of your actions is somewhat vague. Did the BIOS detect the PCIe interface? Did you configure the FPGA after the PC was turned on (in which case it's pretty clear that it doesn't work)?

When you say that you implemented the sample design, was it just load the design into the Xilinx tools, and implement? Or did you make any changes?
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Re: FPGA gives a "unknown header type 7f" with lspci command

Postby Guest » Thu Jul 18, 2019 9:37 am

Hi,

I also have the same problem.

1. Yes, the BIOS detected the PCIe interface.
2. I configured the FPGA before the PC was turned on.
3. It works if I configure the 7 series Integrated Block for PCI Express (3.3) FPGA IP core for gen1 (2.5GT/s). Does not work if it is configure it for gen2 (5.0GT/s).

Can you provide me a solution to this problem please?

Thank you.
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Re: FPGA gives a "unknown header type 7f" with lspci command

Postby support » Thu Jul 18, 2019 10:29 am

Hello,

First of all, it's not clear why you want to configure the PCIe block above Gen1. If you're using a demo bundle with the board it's intended for, that will not improve your bandwidth.

But since you have done that -- did you follow section 4.5 of the Getting started with the FPGA demo bundle for Xilinx?

http://xillybus.com/downloads/doc/xilly ... xilinx.pdf

Changing the attributes of the PCIe block may require additional steps on some FPGA targets, or the PCIe interface becomes unstable.

Regards,
Eli
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Re: FPGA gives a "unknown header type 7f" with lspci command

Postby Guest » Fri Jul 19, 2019 1:11 am

Hi Eli,

Thanks for pointing out section 4.5 of the document. I will try it out.

May I know whether revB Xillybus FPGA bundles are also set as Gen1 (2.5GT/s) by default?

Thanks
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Re: FPGA gives a "unknown header type 7f" with lspci command

Postby support » Fri Jul 19, 2019 2:53 am

Hello,

The bundles are set up with the lowest link speed that matches the IP core's capabilities. As each Gen1 lane gives approximately 200 MB/s, and a rev B IP core is limited to 1600 MB/s, there is no point going faster than Gen1 for a x8 board.

Regards,
Eli
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Re: FPGA gives a "unknown header type 7f" with lspci command

Postby Guest » Fri Jul 19, 2019 8:18 am

Hi,

Ok thanks for your reply. I've implemented the recommendations in section 4.5 and section 5.0 of the document.
However, I still cannot get the bundle design to work for Gen2 (5.0GT/s).

I've also tried the example design from Xilinx and my PC successfully enumerated the FPGA device as Gen2 with no "unknown header type 7f" problem.

Is there something else that I'm missing?

Thanks
Guest
 

Re: FPGA gives a "unknown header type 7f" with lspci command

Postby support » Fri Jul 19, 2019 10:37 am

Hello,

It sounds like you didn't update the timing constraints correctly. If you did, please verify that Vivado is actually consuming the timing constraint file you edited (e.g. by deliberately making an error in it).

As for comparing with Xilinx' example project: Did you try the example project that is generated from the PCIe block in the Xillybus bundle, or some project provided by Xilinx as something to download and run? If the latter, definitely try the former.

Regards,
Eli
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Re: FPGA gives a "unknown header type 7f" with lspci command

Postby Guest » Mon Jul 22, 2019 1:00 am

Hi Eli,

Ok thank you, I will try to update the timing constraints.

Yes, for the Xilinx's example project I generated it from the PCIe block in the Xillybus bundle.
Guest
 

Re: FPGA gives a "unknown header type 7f" with lspci command

Postby Guest » Tue Jul 23, 2019 1:32 am

Hi Eli,

I've verified that Vivado consumed the timing constraints correctly. I've even used the timing constraints from the working Vivado example project on the Xillybus bundle project to no avail - no problem for Gen1 but gives "unknown header type 7f" for Gen2.

Do you have any other suggestions?
Guest
 

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