Parallel access over PCI-E with Xillybus

Questions and discussions about the Xillybus IP core and drivers

Parallel access over PCI-E with Xillybus

Postby Guest »

As far as I understand Xillybus is all about transferring data. But what if I need to access other functionality on FPGA (under linux), for example control & status registers. Could it interfere with the driver or Xillybus as a whole?
Should I perhaps to set up a separate BAR for that?
Guest
 

Re: Parallel access over PCI-E with Xillybus

Postby support »

Hello,

Xillybus allows you to create custom IP cores, with a virtually arbitrary number of separate and independent device files. Some can be used for transmitting application data, and others for control. You may use seekable streams to access registers on the FPGA, or create simple protocols where the host reads or writes a fixed number of bytes for status and control. Or pick any other way that is convenient to convey such information.

In short, odds are that Xillybus covers all your needs.

Regards,
Eli
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Re: Parallel access over PCI-E with Xillybus

Postby Guest »

Are the device use options described anywhere in detail? They obviously generate different interfaces.
I can't decide whether "Xillybus covers all my needs" if I don't know what they do.
Guest
 

Re: Parallel access over PCI-E with Xillybus

Postby support »

Hello,

There's plenty of documentation available on this page:

http://xillybus.com/doc

That said, I suggest downloading a demo bundle for your FPGA family and try it out, following the relevant Getting Started guide. Doing that usually answers the vast majority of questions on what Xillybus is about and how it works.

Regards,
Eli
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Re: Parallel access over PCI-E with Xillybus

Postby Guest »

Thank you, I've already read most of it and it's insufficient.
Only FIFO and memory/address interfaces are anyhow mentioned in the documentation, and you wouldn't get to know that others exist at all from it.

A proper documentation would have:
  • Contain a descrption of each device option (purpose, general function...) in the "the guide to defining a custom Xillybus IP core"
  • Contain detailed description of function and signals in the FPGA designer’s guide.
In this regard you seem to suffer from the curse of knowledge, that everything seem obvious and self-explanatory to you as the designer of the core. But I would really like to ask you to improve on these points. Those device options just show up in the core factory with little to no explanation.

Also I have a data acquisition system and I need to configure the external hardware like PLLs over AXILite. I could try the AXI Datamover for that, but it would be a great help if Xillybus had an AXILite Master device option.

Thank you in advance for your assistance
Guest
 

Re: Parallel access over PCI-E with Xillybus

Postby support »

Hello,

The suggested flow for learning about Xillybus is to download the demo bundle (and driver if necessary), and to try it out, following the relevant guides. It's a fairly quick process, and after playing around a bit with it, most people have an idea about how to use it for their application.

The documentation is written with this flow in mind. Alone, it might indeed appear to be lacking.

The IP core indeed supplies just FIFOs and memory/address interfaces. It's up to each to write the glue logic for the desired application. The usage options in the IP Core Factory are merely intended to configure the stream to work intuitively in the context of a specific use, but this doesn't change the interface. The function and signals are same for all, only with a slightly different behavior (which is documented).

As for AXI Lite master, Xillybus offers no specific interface for that.

Regards,
Eli
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