Re: Xillybus bandwidth can't reach more than 75MB/s
Posted: Hi,
Just a final check: The bundle's readme file requires that ISE 13.1 is used to generate Xilinx' PCIe IP core (so that the version of PCIe Block Plus generator is 1.14). Just wanted to confirm that you followed that.
Regards,
Eli
Just a final check: The bundle's readme file requires that ISE 13.1 is used to generate Xilinx' PCIe IP core (so that the version of PCIe Block Plus generator is 1.14). Just wanted to confirm that you followed that.
Regards,
Eli