PCIe data rate

Questions and discussions about the Xillybus IP core and drivers

PCIe data rate

Postby svedach »

Hello, I'm just interested in improving tire performance between the FIFO and the core. Is addressing the problem of obtaining long-term continuous recording with high-speed ADC and used on board has little memory DDR. Now I use KC705. Required clock speed 32-bit bus at least 350-400MHz (by the way, notice that you have a chain with 18 logic levels, longish, and it limits the maximum clock frequency).
You developed the core is simply wonderful.
svedach
 
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Re: PCIe data rate

Postby support »

Hello,

I'm glad that you liked the overall design of Xillybus.

Xillybus' data rates are discussed on this page: http://xillybus.com/doc/xillybus-bandwidth

As for rates, with 32 bits at 400 MHz, we're looking at some 1.6 GB/s. I don't know what kind of computer you have there, but most computers will have a difficulty to do anything meaningful with much lower data rates. I suggest trying to consume data from /dev/zero or something, and see what rate your computer can maintain. Note that if you try copying to disk, the initial speed will be fantastic because the data is just being stored in the disk cache. Let it run for a while...

If you really have a useful real-life data sink that you can verify consuming more than the 800 MB/s that KC705 is capable of with Xillybus, I'm curious to know about it. Up to this point, the reason Xillybus isn't sped up, is because the real-life applications are way behind.

Regards,
Eli
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Re: PCIe data rate

Postby svedach »

Thanks for the quick reply.
This speed is necessary, as the original data will be accumulated in the unfragmented RAM, hard drive, we use solid state. Believe me, this speed is really necessary.
svedach
 
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Re: PCIe data rate

Postby support »

I can see the advantage of storing a large amount of data in the host's RAM and then store it slowly into permanent media. On the other hand, the board's own SODIMM can be used for storing the data temporarily (even though it's probably more limited in size), and then piped through at a slower pace for storage.

As for solid state disks -- that's really interesting. What device do you have there, and what rates have you measured on it?

Regards,
Eli
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Re: PCIe data rate

Postby svedach »

We're going to discuss the basic question - is it possible to increase the speed of data transfer between the FIFO and the kernel, such as the expansion of the data bus to 64 or even 128-bit, or increase the clock frequency. Believe me, there is a use for this. About SSD, carefully and measure and tell the results.
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Re: PCIe data rate

Postby support »

Hi,

Making the data bus wider, for the sake of increasing the bandwidth, is a task that has been on Xillybus' roadmap for a long time, but the priorities are set according to what is actually used by paying licensees. This is why I'm interested to know if there's a real use of more than 800 MB/s.

Regards,
Eli
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