EOF Error

Questions and discussions about the Xillybus IP core and drivers

EOF Error

Postby ali »

Hello,

We are trying Xillybus PCIe environment on Spartan 6 LXT based system.

We changed demo project a little bit.
- If demoarray[0] equals to 0xFF then fifo32 is written 4 times in a second with dummy data.

In first console we call "streamread \\.\xillybus_read_32" command.
In a different console we write demoarray[0] 0xFF using "memwrite \\.\xillybus_mem_8 0 255" command.
After that the first terminal starts listing received data.

In 64bit Linux system, it works well. But in 64 bit Windows 7, it stops with "Reached read EOF." error message after some transfer between 12 - 250 transfer.

Not immediately after the error but sometimes following error message appears on "Event Viewer"
- xillybus: Failed to quiesce the device on exit.
- xillybus: Quitting while leaving a mess.

How can we solve the problem?

Regards,
Ali
ali
 
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Re: EOF Error

Postby support »

Hello,

I see two distinct problems here. One,
ali wrote:In 64bit Linux system, it works well. But in 64 bit Windows 7, it stops with "Reached read EOF." error message after some transfer between 12 - 250 transfer.

It should work exactly the same on Linux and Windows. The difference is probably a tiny difference in latencies caused by the operating systems.

Anyhow, you didn't mention asserting any of the *_eof signals in the logic, so there is no reason why you should see an EOF on the host.

ali wrote:Not immediately after the error but sometimes following error message appears on "Event Viewer"
- xillybus: Failed to quiesce the device on exit.
- xillybus: Quitting while leaving a mess.

This is a serious error. The only "natural" explanation is that the FPGA was reconfigured or lost power while the computer was on. If nothing of this sort happened, the first thing I'd ask you to verify, is that the timing constraints were met when you implemented the design. It should say "All constraints were met" in the summary window in ISE when bitfile is generated. Can you confirm this?

Best regards,
Eli
support
 
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Re: EOF Error

Postby ali »

Hello,

All *_eof signal values are zero as in the demo design, we didn't change it.

ali wrote:Not immediately after the error but sometimes following error message appears on "Event Viewer"
- xillybus: Failed to quiesce the device on exit.
- xillybus: Quitting while leaving a mess.

This is a serious error. The only "natural" explanation is that the FPGA was reconfigured or lost power while the computer was on.

That's right. We configured Fpga a few times while computer was on. This must be the reason for the error messages as you said.

It should say "All constraints were met" in the summary window in ISE when bitfile is generated. Can you confirm this?

Yes, all timings are met. We checked it. There are only two timing constraints in the ucf file. As a result of these two constraints and maybe other hidden constraints in the cores are met.

By the way, we changed PCIE_250M_P frequency to 100MHz in constraint file and in the PCIe core, because our board's current configuration has 100MHz clock for the PCIe. Could the errors be related to this change? If so, we can change our board's PCIe clock to 125MHz and we can try again with new timing constraints.

Regards,
Ali
ali
 
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Re: EOF Error

Postby support »

Hi,

First of all, if you configure the FPGA while the computer is running (that is, powered on and in a non-reset state), anything can happen. It's true that one usually gets away with this, but no computer expects the PCIe link to suddenly go away and then come back, so its reaction is unpredictable.

The second issue is the clock -- working with a different clock frequency is fine, as long as its clean enough per Xilinx' spec and derived from the PCIe bus' reference clock. If you're using your own on-board free-running oscillator for running Xilinx' PCIe IP core, everything becomes unstable.

I should mention the Xillybus is being widely used and proved to be rock stable based upon various pieces of hardware. We're not looking for a slight tuning, given the kind of problems you're reporting. Something is seriously wrong in your system.

Best regards,
Eli
support
 
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Re: EOF Error

Postby ali »

Hello,

We reprogram the FPGA while the system is running, for testing other parts
of the board. For these PCIe tests, we run them right after a power-cycle
of the PC. Our board has a quad SPI flash, so it meets the 100ms timing
of the PCIe specification. (Otherwise the system would probably not see
in the first place)

Regarding the clock: Our clock is derived from the PCIe reference clock,
by way of a jitter cleaner IC (ICS874001AGI). This IC is configurable
(it can output 100, 125 or 250MHz). Currently, 100 MHz is selected.

By the way, the test computer is the same for both Linux and Windows (ie, it is
a dual boot system). As I mentioned in the first post, we don't run into any
problems when running on Linux. I would expect that we don't have
"something seriously wrong with our system", since it works without a
problem on the Linux side. In addition, we've used the same board with
other drivers and other software stack and didn't have any stability issues.

Any other ideas? Is there anything we can look at or try which might help
identify what the problem is? For example, we tried writing data into the
FIFO much faster, in which case we get the EOF error even more quickly.

Best,
ali
 
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Re: EOF Error

Postby support »

Hi,

You did use the _O_BINARY flag, right? It must be used in the _open() call in Windows. If this flag isn't used, an 0x1a character in the input stream will be interpreted as an EOF. Maybe this was the cause of this issue.

Best regards,
Eli
support
 
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