canit find xillybus_read_8

Questions and discussions about the Xillybus IP core and drivers

Re: canit find xillybus_read_8

Postby apna »

Hi
thanks..

can we know the performance of PCIe utilized to transfer data in the demo apps for virtex 6?
apna
 
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Re: canit find xillybus_read_8

Postby support »

Hello,

To get an idea of the performance, you first need to untie to loopback in xillydemo, so that there's no link between the data sent to the FPGA and the one that arrives. In fact, it's enough just to make sure that the "empty" and "full" signals that are connected to the loopback FIFO are held zero. It's quite difficult to set up a performance test with data looping back, because the data flow gets stalled all the time.

You may write your own test application, or use the "dd" Linux command. Please note that the block size matters, as this has an influence on the operating system's overhead. Also please note that the write_8/read_8 pair isn't intended for heavy data transmission, and has a quite lousy performance. Go for write_32 and read_32, possibly with a custom IP core which has these configured for data acquisition / playback.

So it's basically something like

dd if=/dev/zero of=/dev/xillybus_write_32 bs=16k

and press CTRL-C after a few seconds. Possibly play with the "bs" parameter a bit. For this to work, the "full" signal on the FPGA must be held zero, which isn't the situation in the demo bundle as it arrives (which is why xillydemo.v/.vhd needs to be edited as mentioned above).

Regards,
Eli
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