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canit find xillybus_read_8

PostPosted:
by apna
Hi....

I was trying to execute the xillybus demoapps for virtex6 ML605 according to the documents but as run "cat /dev/xillybus_read_8"
i got an error message " failed to open the device" also I didnt find xillybus_read_8 in /dev.Should I create a "xillybus_read_8" in /dev?

thank you

Re: canit find xillybus_read_8

PostPosted:
by support
Hello,

The /dev/xillybus_* files appear automatically as driver is loaded with a Xillybus-enabled PCIe interface on the bus. So obviously something didn't go well. The two basic things to check is whether the driver was installed correctly (possibly use insmod/lsmod to load it manually just to be sure it's loaded), and whether the PCIe interface appear on the bus with lspci, looking for a device with ID 10ee:ebeb.

Hope this helps,
Eli

Re: canit find xillybus_read_8

PostPosted:
by apna
thank you eli....

I reprogrammed the FPGA and loaded the driver. Now its working well.

As i tried to execute the FIFO program ,i got the message as

"./fifo 3
0 bytes in FIFO, 0 read, 0 written"

Re: canit find xillybus_read_8

PostPosted:
by support
Hello,

Unless you need really huge buffers (>512MB or so), I don't think you really need to use that utility.

Anyhow, it's not clear exactly what you did, so I can't help you much as is.

Regards,
Eli

Re: canit find xillybus_read_8

PostPosted:
by apna
Hi

I need larger buffer(512-1024),does the demoapp provide any program,for large buffers?

hows the execution of the fifo program given in the demo bundle?

thanks...

Re: canit find xillybus_read_8

PostPosted:
by support
Hello,

Please generate your custom IP core in the IP Core Factory: http://xillybus.com/custom-ip-factory

Also, please refer to the getting started and programming guides for more information about how to interact with the device files. It's all down to basic reading and writing to files.

Regards,
Eli

Re: canit find xillybus_read_8

PostPosted:
by apna
Hi..

I had generated the ip core according to my requirements and followed the steps in the "xillybus_getting_started_xilinx.pdf",but as i started the "Generate Programming File” to implement, i got the following errors...


Elaborating module <xillybus_core>.
WARNING:HDLCompiler:1499 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillybus_core.v" Line 1: Empty module <xillybus_core> remains a black box.
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 63: Cannot find port user_r_mem_8_rden on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 64: Cannot find port user_r_mem_8_empty on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 65: Cannot find port user_r_mem_8_data on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 66: Cannot find port user_r_mem_8_eof on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 67: Cannot find port user_r_mem_8_open on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 70: Cannot find port user_w_mem_8_wren on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 71: Cannot find port user_w_mem_8_full on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 72: Cannot find port user_w_mem_8_data on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 73: Cannot find port user_w_mem_8_open on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 76: Cannot find port user_mem_8_addr on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 77: Cannot find port user_mem_8_addr_update on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 82: Cannot find port user_r_read_32_rden on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 83: Cannot find port user_r_read_32_empty on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 84: Cannot find port user_r_read_32_data on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 85: Cannot find port user_r_read_32_eof on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 86: Cannot find port user_r_read_32_open on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 90: Cannot find port user_w_write_32_wren on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 91: Cannot find port user_w_write_32_full on this module
ERROR:HDLCompiler:267 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 92: Cannot find port user_w_write_32_data on this module
Sorry, too many errors..
WARNING:HDLCompiler:1499 - "C:\Users\Administrator\Downloads\xillybus-eval-virtex6-1.2\xillybus-eval-virtex6-1.2\verilog\src\xillydemo.v" Line 1: Empty module <xillydemo> remains a black box.


what could be the reason for this ? i have copied all the newly generated files to the demo bundle.

thanks.

Re: canit find xillybus_read_8

PostPosted:
by support
Hello,

Please refer to the README.TXT file that is included in the custom IP core bundle. In particular this item in the instructions:
(3) Edit xillydemo.v (or xillydemo.vhd) to reflect the desired application
of this custom IP core. The template.v (or template.vhd) file in the
"instantiation templates" directory of this bundle contains the signal
outline and instantion format.


It looks like you didn't edit your Xillydemo file correctly or at all.

Regards,
Eli

Re: canit find xillybus_read_8

PostPosted:
by apna
Hi

As I edited xillydemo.v,the problem was solved ...thanks :)

i want to edit the streamwrite program to write data from a file to console instead of writing directly to console ,what changes need to be made to the streamwrite program to attain this.

thank you.

Re: canit find xillybus_read_8

PostPosted:
by support
Hi,
apna wrote:i want to edit the streamwrite program to write data from a file to console instead of writing directly to console ,what changes need to be made to the streamwrite program to attain this.

Why don't you just use streamread? It does exactly that: Reads from a file, outputs to stdout.

Regards,
Eli