fifo.c integration

Questions and discussions about the Xillybus IP core and drivers

fifo.c integration

Postby Guest »

I am having issues with incorporating the fifo.c example (from xillybus) into a C++ program that I have currently writing to a file. I need to modify my C++ program so that it uses the FIFO to write to memory continuously and later read from from it. I know from reading the host programming guide for Linux that it is the FIFO I need to use in order to have a continuous high rate I/O. Could I receive some help on how to utilize the fifo.c to write to and from memory continuously?
Thanks
Alejandro
Guest
 

Re: fifo.c integration

Postby support »

Hello,

The programming guide pretty much outlines how to interact with the code for custom modifications. Can you point at any specific difficulty?

And since we're at it, I'd like to point out that odds are that you don't really need fifo.c. In all but very few cases, you can define a custom IP core at the IP Core Factory that gives DMA buffers which are large enough for maintaining continuous I/O. It's also a safer way, since the DMA flow is completely independent on what the host does. There should be no problem to get a hold of 512 MB or so of total DMA buffer space. Do you need more than that?

Regards,
Eli
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Re: fifo.c integration

Postby alejandro »

I have read through all the documentation found on xillybus. I found http://e-archivo.uc3m.es/bitstream/hand ... sequence=1 and host programming guide for Linux on the xillbus website to be really helpful. However, it is a little too high level for me. I see frequent phrases of simply connecting the FIFO and setting a flag for an asynchronous stream. I do not know where to do this.
Currently I have a C++ program that is saving a stream to a .dat file. The big picture of what I need to do is edit my C++ program to use the FIFO in order to save to memory in an asynchronous stream. From there, the data needs to be read from memory in a FIFO and taken to another program to be processed (while always trying to maintain the memory at 50% full). Finally that program that processes the data will send the output from it to a pin on a PMOD.
I know that is the whole purpose of Xillybus. I am confused as to whether I am supposed to edit the xillybus.v file or if I edit my C++ program in order to connect the FIFO. I also do not know where the asynchronous stream flag is set as outlined in the documentation on xillybus. I did change my C++ program to write to /dev/xillybus_write_8 and from what I understood, that writes it to memory through a FIFO. I do not know how to read from it to confirm my thought.
As for the custom IP core, I went to the IP Core Factory and could only find the following options (with my answers included):
IP core's name: myipcore
Target device family: Xilinx Zynq-7000 (ZyBo)
Initial template: Demo Bundle Setting

I do not see where the DMA buffer is defined at the IP Core Factory. But you are correct, 512 MB of total DMA buffer space should be fine. I just don't understand how to define that on the IP custom core.

Thanks for all the help. I greatly the extra help
Alejandro
alejandro
 
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Re: fifo.c integration

Postby Guest »

I have figured out how to use the custom IP core factory but I am still unsure of which file I need to edit in order to attach the FIFOs. I am not sure if that would be down in the C++ program or the xillydemo.v
Guest
 

Re: fifo.c integration

Postby support »

Hello,

What I suggest at this stage, is leaving the IP Core Factory for now and just work with the demo bundle as is. If you have buffering problems in the future, get yourself a core with a larger DMA buffer. At that stage, it will be easy. Neither should you bother yourself with asynchronous vs. synchronous streams at the moment.

Writing your data to /dev/xillybus_write_8 was a step in the right direction. The next step is to edit xillydemo.v or xillydemo.vhd (depending on your favorite language) and connect your desired FIFO instead of the one looping back from write_8 to read_8. If you're not familiar with FPGA design concepts, I suggest taking some time to widen your knowledge in Verilog (or VHDL) and also the concept of a hardware FIFO. With basic RTL coding skills, you should be able to get the data out to the PMOD.

So what I suggest is to have the PMOD talking with you, and then solve any possible data flow issues.

Regards,
Eli
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FIFO, IP core factory, data acquisition, and ZyBo board

Postby Guest »

How do you do a asynchronous data acquisition? I am a bit confused because it appears on the IP core factory that it is just an asynchronous flag. However, on reading http://www.xillybus.com/downloads/doc/x ... ga_api.pdf in chapter 4 it discusses "implementing data acquisition". I am currently working with a ZyBo board which has the zynq 7000. In this section it says I need to use xillycapture.v and an additional coregen file. Do I need to run the runonce file again including the coregen file and would I use the file for the spartan 6? Also would I integrate the logic from the xillycapture.v into my xillydemo.v? Overall I am not sure what needs to be done for asynchronous, continuous data acquisition FIFO with a width of 32bits (host to FPGA) and if that requires some type of formatting with xillycapture?
Thanks
Guest
 

Re: fifo.c integration

Postby support »

Hello,

The "xillycapture" is given just as an example of how to implement data acquisition, which is why it's targeted for a number of FPGAs only (Spartan 6 in particular). The point is to adopt the ideas, not necessarily copy the code as is. In the end of the day, there's no choice but to understand what we're doing. ;)

"Asynchronous" in this context is a Xillybus' stream attribute, which relates to its flow control. It's explained extensively in section 2 of either programming guides. Please take a look. Where it says "asynchronous FIFO", that means a FIFO with two independent clocks, which is necessary if the data is clocked with another clock than bus_clk. In that case, create a new FIFO with Coregen in the main project, and instantiate it into the design -- just like any Coregen IP core.

Regards,
Eli
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