I have read through all the documentation found on xillybus. I found
http://e-archivo.uc3m.es/bitstream/hand ... sequence=1 and host programming guide for Linux on the xillbus website to be really helpful. However, it is a little too high level for me. I see frequent phrases of simply connecting the FIFO and setting a flag for an asynchronous stream. I do not know where to do this.
Currently I have a C++ program that is saving a stream to a .dat file. The big picture of what I need to do is edit my C++ program to use the FIFO in order to save to memory in an asynchronous stream. From there, the data needs to be read from memory in a FIFO and taken to another program to be processed (while always trying to maintain the memory at 50% full). Finally that program that processes the data will send the output from it to a pin on a PMOD.
I know that is the whole purpose of Xillybus. I am confused as to whether I am supposed to edit the xillybus.v file or if I edit my C++ program in order to connect the FIFO. I also do not know where the asynchronous stream flag is set as outlined in the documentation on xillybus. I did change my C++ program to write to /dev/xillybus_write_8 and from what I understood, that writes it to memory through a FIFO. I do not know how to read from it to confirm my thought.
As for the custom IP core, I went to the IP Core Factory and could only find the following options (with my answers included):
IP core's name: myipcore
Target device family: Xilinx Zynq-7000 (ZyBo)
Initial template: Demo Bundle Setting
I do not see where the DMA buffer is defined at the IP Core Factory. But you are correct, 512 MB of total DMA buffer space should be fine. I just don't understand how to define that on the IP custom core.
Thanks for all the help. I greatly the extra help
Alejandro