Writing data to FPGA FIFO from host program
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We are having issues with transferring our program data to the FIFO on the FPGA. The FIFO is not receiving the correct data from the program. We tested our Verilog code by hard coding the data into the FIFO and we received the correct data output results. However, when we replace the hard coded data input to the FIFO with the host program data wire, user_w_write_32_data, we get a seemingly random output. For testing purposes, we made are host program data a 32bit 1's in a couple of different forms as shown below in our code. We expect our output to be a 32bit sequence of all 1's on the FPGA but our output sequence is 00110110001110010011010000111001.
Thank you very much for your assistance.
- Code: Select all
std::ofstream FIFO;
FIFO.open("/dev/xillybus_write_32");
uint32_t output32 = 0; //Linux unsigned 32bit number
while(1){
//output32 = 4294967295; //decimal equivalent of 32bit binary 1's. This is the format that we would like to put into the FIFO //First attempt
//output32 = 0b11111111111111111111111111111111; //32bit binary 1's. (Same as above statement) //Second Attempt
//FIFO << output32; //push output32 to FIFO
FIFO << 0b11111111111111111111111111111111; //pushing 32bit 1's straight into FIFO// Third Attempt
}
if (FIFO.is_open()){
FIFO.close();
}
Thank you very much for your assistance.