Speed of writing data from host program to FPGA FIFO
Posted:
Hi,
I am continuously writing 32 bits from the host program to the FPGA FIFO. My Verilog code has to wait a while after it is done clocking the bits out to pins before the FIFO is not empty and it can grab the next 32 bits. I am passing the data into the FPGA FIFO from my host program in the following manner;
Do you know how fast we can write data to the FPGA FIFO using Xillybus, (/dev/xillybus_write_32)? Do you happen to know of any ways to make that process faster? Any help or reference to documentation would be much appreciated. Thank you very much!
I am continuously writing 32 bits from the host program to the FPGA FIFO. My Verilog code has to wait a while after it is done clocking the bits out to pins before the FIFO is not empty and it can grab the next 32 bits. I am passing the data into the FPGA FIFO from my host program in the following manner;
- Code: Select all
std::ofstream FIFO;
FIFO.open("/dev/xillybus_write_32", std::ofstream::binary);
while(1){
output32 = 4294967295;
FIFO.write((char *)&output32, sizeof(output32));
}
Do you know how fast we can write data to the FPGA FIFO using Xillybus, (/dev/xillybus_write_32)? Do you happen to know of any ways to make that process faster? Any help or reference to documentation would be much appreciated. Thank you very much!