[Synth 8-493] no such design unit 'sw_fifo'

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[Synth 8-493] no such design unit 'sw_fifo'

Postby Guest »

Hi,
i wish to ask you a doubt. I wrote a code but I am getting an error "[Synth 8-493] no such design unit 'sw_fifo' ". I have added the code below. Can anyone please help me.

library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_unsigned.all;
--use IEEE.numeric_std.all;

entity xillydemo is

port (
switches : IN std_logic;
leds : OUT std_logic
-- -- For Vivado, delete the port declarations for PS_CLK, PS_PORB and
-- -- PS_SRSTB (possibly removing this "port" clause completely if it ends
-- -- up empty), and uncomment their declarations as signals further below.

-- PS_CLK : IN std_logic;
-- PS_PORB : IN std_logic;
-- PS_SRSTB : IN std_logic
);
end xillydemo;

architecture sample_arch of xillydemo is
component xillybus
port (
DDR_Addr : INOUT std_logic_vector(14 DOWNTO 0);
DDR_BankAddr : INOUT std_logic_vector(2 DOWNTO 0);
DDR_CAS_n : INOUT std_logic;
DDR_CKE : INOUT std_logic;
DDR_CS_n : INOUT std_logic;
DDR_Clk : INOUT std_logic;
DDR_Clk_n : INOUT std_logic;
DDR_DM : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQ : INOUT std_logic_vector(31 DOWNTO 0);
DDR_DQS : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DQS_n : INOUT std_logic_vector(3 DOWNTO 0);
DDR_DRSTB : INOUT std_logic;
DDR_ODT : INOUT std_logic;
DDR_RAS_n : INOUT std_logic;
DDR_VRN : INOUT std_logic;
DDR_VRP : INOUT std_logic;
MIO : INOUT std_logic_vector(53 DOWNTO 0);
DDR_WEB : OUT std_logic;
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
user_r_mem_8_rden : OUT std_logic;
user_r_mem_8_empty : IN std_logic;
user_r_mem_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_mem_8_eof : IN std_logic;
user_r_mem_8_open : OUT std_logic;
user_w_mem_8_wren : OUT std_logic;
user_w_mem_8_full : IN std_logic;
user_w_mem_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_mem_8_open : OUT std_logic;
user_mem_8_addr : OUT std_logic_vector(4 DOWNTO 0);
user_mem_8_addr_update : OUT std_logic;
user_r_read_32_rden : OUT std_logic;
user_r_read_32_empty : IN std_logic;
user_r_read_32_data : IN std_logic_vector(31 DOWNTO 0);
user_r_read_32_eof : IN std_logic;
user_r_read_32_open : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_32_wren : OUT std_logic;
user_w_write_32_full : IN std_logic;
user_w_write_32_data : OUT std_logic_vector(31 DOWNTO 0);
user_w_write_32_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic;
user_clk : OUT std_logic;
user_wren : OUT std_logic;
user_wstrb : OUT std_logic_vector(3 DOWNTO 0);
user_rden : OUT std_logic;
user_rd_data : IN std_logic_vector(31 DOWNTO 0);
user_wr_data : OUT std_logic_vector(31 DOWNTO 0);
user_addr : OUT std_logic_vector(31 DOWNTO 0);
user_irq : IN std_logic);

end component;

component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;

component fifo_32x512
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(31 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(31 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;

-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_32x512: component is true;
attribute syn_black_box of fifo_8x2048: component is true;

type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal demoarray : demo_mem;
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;

signal bus_clk : std_logic;
signal quiesce : std_logic;

signal reset_8 : std_logic;
signal reset_32 : std_logic;

signal ram_addr : integer range 0 to 31;
signal lite_addr : integer range 0 to 31;

signal user_r_mem_8_rden : std_logic;
signal user_r_mem_8_empty : std_logic;
signal user_r_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_mem_8_eof : std_logic;
signal user_r_mem_8_open : std_logic;
signal user_w_mem_8_wren : std_logic;
signal user_w_mem_8_full : std_logic;
signal user_w_mem_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_mem_8_open : std_logic;
signal user_mem_8_addr : std_logic_vector(4 DOWNTO 0);
signal user_mem_8_addr_update : std_logic;
signal user_r_read_32_rden : std_logic;
signal user_r_read_32_empty : std_logic;
signal user_r_read_32_data : std_logic_vector(31 DOWNTO 0);
signal user_r_read_32_eof : std_logic;
signal user_r_read_32_open : std_logic;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_32_wren : std_logic;
signal user_w_write_32_full : std_logic;
signal user_w_write_32_data : std_logic_vector(31 DOWNTO 0);
signal user_w_write_32_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal user_clk : std_logic;
signal user_wren : std_logic;
signal user_wstrb : std_logic_vector(3 DOWNTO 0);
signal user_rden : std_logic;
signal user_rd_data : std_logic_vector(31 DOWNTO 0);
signal user_wr_data : std_logic_vector(31 DOWNTO 0);
signal user_addr : std_logic_vector(31 DOWNTO 0);
signal user_irq : std_logic;

-- Data capture
signal capture_clk : std_logic;
signal capture_data : std_logic;
signal capture_en : std_logic;
signal capture_full : std_logic;
signal capture_has_been_full : std_logic;
signal capture_has_been_nonfull : std_logic;
signal capture_open : std_logic;
signal capture_open_cross : std_logic;
signal has_been_full : std_logic;
signal has_been_full_cross : std_logic;
signal sw_reset_8 : std_logic;

-- Data writing
signal writing_clk : std_logic;
signal writing_data : std_logic;
signal writing_en : std_logic;
signal writing_full : std_logic;
signal writing_has_been_full : std_logic;
signal writing_has_been_nonfull : std_logic;
signal writing_open : std_logic;
signal writing_open_cross : std_logic;
signal w_has_been_full : std_logic;
signal w_has_been_full_cross : std_logic;
signal leds_reset8 : std_logic;
signal leds_fifo_empty : std_logic;
signal leds_read_enable : std_logic;
signal writing_rst : std_logic;

-- Note that none of the ARM processor's direct connections to pads is
-- defined as I/O on this module. Normally, they should be connected
-- as toplevel ports here, but that confuses Vivado 2013.4 to think that
-- some of these ports are real I/Os, causing an implementation failure.
-- This detachment results in a lot of warnings during synthesis and
-- implementation, but has no practical significance, as these pads are
-- completely unrelated to the FPGA bitstream.

signal PS_CLK : std_logic;
signal PS_PORB : std_logic;
signal PS_SRSTB : std_logic;
signal DDR_Addr : std_logic_vector(14 DOWNTO 0);
signal DDR_BankAddr : std_logic_vector(2 DOWNTO 0);
signal DDR_CAS_n : std_logic;
signal DDR_CKE : std_logic;
signal DDR_CS_n : std_logic;
signal DDR_Clk : std_logic;
signal DDR_Clk_n : std_logic;
signal DDR_DM : std_logic_vector(3 DOWNTO 0);
signal DDR_DQ : std_logic_vector(31 DOWNTO 0);
signal DDR_DQS : std_logic_vector(3 DOWNTO 0);
signal DDR_DQS_n : std_logic_vector(3 DOWNTO 0);
signal DDR_DRSTB : std_logic;
signal DDR_ODT : std_logic;
signal DDR_RAS_n : std_logic;
signal DDR_VRN : std_logic;
signal DDR_VRP : std_logic;
signal MIO : std_logic_vector(53 DOWNTO 0);
signal DDR_WEB : std_logic;
--signal FCLK_CLK0_INT:STD_LOGIC;
--signal FCLK_CLK0:STD_LOGIC;
--signal dac_data : std_logic_vector(7 downto 0);
-- signal counter : unsigned (24 downto 0);

begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_mem_8
-- FPGA to CPU signals:
user_r_mem_8_rden => user_r_mem_8_rden,
user_r_mem_8_empty => user_r_mem_8_empty,
user_r_mem_8_data => user_r_mem_8_data,
user_r_mem_8_eof => user_r_mem_8_eof,
user_r_mem_8_open => user_r_mem_8_open,
-- CPU to FPGA signals:
user_w_mem_8_wren => user_w_mem_8_wren,
user_w_mem_8_full => user_w_mem_8_full,
user_w_mem_8_data => user_w_mem_8_data,
user_w_mem_8_open => user_w_mem_8_open,
-- Address signals:
user_mem_8_addr => user_mem_8_addr,
user_mem_8_addr_update => user_mem_8_addr_update,

-- Ports related to /dev/xillybus_read_32
-- FPGA to CPU signals:
user_r_read_32_rden => user_r_read_32_rden,
user_r_read_32_empty => user_r_read_32_empty,
user_r_read_32_data => user_r_read_32_data,
user_r_read_32_eof => user_r_read_32_eof,
user_r_read_32_open => user_r_read_32_open,

-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,

-- Ports related to /dev/xillybus_write_32
-- CPU to FPGA signals:
user_w_write_32_wren => user_w_write_32_wren,
user_w_write_32_full => user_w_write_32_full,
user_w_write_32_data => user_w_write_32_data,
user_w_write_32_open => user_w_write_32_open,

-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,

-- Ports related to Xillybus Lite
user_clk => user_clk,
user_wren => user_wren,
user_wstrb => user_wstrb,
user_rden => user_rden,
user_rd_data => user_rd_data,
user_wr_data => user_wr_data,
user_addr => user_addr,
user_irq => user_irq,


-- General signals
-- PS_CLK => PS_CLK,
-- PS_PORB => PS_PORB,
-- PS_SRSTB => PS_SRSTB,
DDR_Addr => DDR_Addr,
DDR_BankAddr => DDR_BankAddr,
DDR_CAS_n => DDR_CAS_n,
DDR_CKE => DDR_CKE,
DDR_CS_n => DDR_CS_n,
DDR_Clk => DDR_Clk,
DDR_Clk_n => DDR_Clk_n,
DDR_DM => DDR_DM,
DDR_DQ => DDR_DQ,
DDR_DQS => DDR_DQS,
DDR_DQS_n => DDR_DQS_n,
DDR_DRSTB => DDR_DRSTB,
DDR_ODT => DDR_ODT,
DDR_RAS_n => DDR_RAS_n,
DDR_VRN => DDR_VRN,
DDR_VRP => DDR_VRP,
MIO => MIO,
DDR_WEB => DDR_WEB,
bus_clk => bus_clk,
quiesce => quiesce
);
--flash_led_counter : process(bus_clk, counter)
-- begin
--if rising_edge(bus_clk) then
-- counter <= counter + 1; -- Will roll over to 0 when it reaches 2^25-1
--end if;
-- end process;

--led_plus <= counter(24);

-- Xillybus Lite

user_irq <= '0'; -- No interrupts for now
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));

process (user_clk)
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;

if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;

if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;

if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;

if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
end if;
end process;

-- A simple inferred RAM

ram_addr <= conv_integer(user_mem_8_addr);

process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
end if;
end if;
end process;

user_r_mem_8_empty <= '0';
user_r_mem_8_eof <= '0';
user_w_mem_8_full <= '0';

-- 32-bit loopback

fifo_32 : fifo_32x512
port map(
clk => bus_clk,
srst => reset_32,
din => user_w_write_32_data,
wr_en => user_w_write_32_wren,
rd_en => user_r_read_32_rden,
dout => user_r_read_32_data,
full => user_w_write_32_full,
empty => user_r_read_32_empty
);

reset_32 <= not (user_w_write_32_open or user_r_read_32_open);

user_r_read_32_eof <= '0';

-- 8-bit loopback

--fifo_8 : fifo_8x2048
-- port map(
--clk => bus_clk,
--srst => reset_8,
--din => user_w_write_8_data,
--wr_en => user_w_write_8_wren,
--rd_en => user_r_read_8_rden,
--dout => user_r_read_8_data,
--full => user_w_write_8_full,
--empty => user_r_read_8_empty
--);

--reset_8 <= not (user_w_write_8_open or user_r_read_8_open);

--user_r_read_8_eof <= '0';

capture_data <= switches;

inst_sw_fifo : sw_fifo
PORT MAP (
rst => sw_reset_8,
wr_clk => capture_clk,
rd_clk => bus_clk,
din => capture_data,
wr_en => capture_en,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => capture_full,
empty => user_r_read_8_empty
);

-- data capture should not take place if the FIFO is full, as FIFO will not be refilled
capture_en <= capture_open and not capture_full and not capture_has_been_full;

-- work out when capture has been full: if capture_full goes high, has been does
-- when file is closed, has been full goes low
work_out_if_has_been_full: process(capture_clk)
begin
if rising_edge(capture_clk) then
if capture_full = '0' then -- capture isn't full
capture_has_been_nonfull <= '1';
elsif capture_open = '0' then -- capture isn't open: must have filled up
capture_has_been_nonfull <= '0';
end if;

if (capture_full = '1' and capture_has_been_nonfull = '1') then -- just filled up
capture_has_been_full <= '1';
elsif capture_open = '0' then -- capture has been closed
capture_has_been_full <= '0';
end if;

end if;
end process;

-- generate an end of file when the FIFO is exhausted, and will not be refilled as it has been full
user_r_read_8_eof <= user_r_read_8_empty and has_been_full; -- has_been_full is capture_has_been_full
-- after crossing clock domain


capture_clk <= bus_clk;

sw_reset_8 <= not user_r_read_8_open;

-- LEDs logic is still to be done, but just to get a bitstream:
--leds <= (others => '0');
leds_fifo : sw_fifo
PORT MAP (
rst => writing_rst,
wr_clk => writing_clk,
rd_clk => bus_clk,
din => user_w_write_8_data,
wr_en => user_w_write_8_wren,
rd_en => leds_read_enable,
dout => leds,
full => user_w_write_8_full,
empty => leds_fifo_empty
);

-- FIFO is reset when the file is closed
writing_rst <= not user_w_write_8_open;
-- Writing clock is just bus clock
writing_clk <= bus_clk;

leds_rd_en: process(bus_clk)
begin
if rising_edge(bus_clk) then
leds_read_enable <= not leds_fifo_empty and user_w_write_8_open;
end if;
end process;

end sample_arch;
Guest
 

Re: [Synth 8-493] no such design unit 'sw_fifo'

Postby support »

Hello,

It looks like you expect a FIFO named sw_fifo to be in your design. To have one, open the IP Catalog, and use the FIFO Generator under Memory & Storage Elements > FIFOs.

Regards,
Eli
support
 
Posts: 802
Joined:

Re: [Synth 8-493] no such design unit 'sw_fifo'

Postby jja »

Thanks Eli. I opened the FIFO genertor and now i got a block with FIFO_WRITE, FIFO_READ, clk and rst. Do I need to do anything in that. Also do I need to change the component Name to sw_fifo.
jja
 
Posts: 2
Joined:

Re: [Synth 8-493] no such design unit 'sw_fifo'

Postby support »

Hi,

Please refer to Xilinx' documentation on how to generate a FIFO. This is not specific to Xillybus.

Regards,
Eli
support
 
Posts: 802
Joined:


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