Replacing mem with a dual port ram

Questions and discussions about the Xillybus IP core and drivers

Replacing mem with a dual port ram

Postby arash »

Hi Eli,
I am using a vc707 board and trying to replace inferred RAM in the reference design (32 bit) with a Dual Port Ram.
I have used the following code:
-------------------------------------------
my_dpram : dpr_32bx16a
PORT MAP (
clka => bus_clk,
ena => '1',
wea => wea,
addra => user_mem_32_addr,
dina => user_w_mem_32_data,
douta => user_r_mem_32_data,

clkb => dpram_clk,
enb => dpram_en,
web => dpram_we,
addrb => dpram_addr,
dinb => dpram_data_in,
doutb => dpram_data_out
);

process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_32_wren = '1') then
wea(0) <= '1';
end if;
if (user_r_mem_32_rden = '1') then
wea(0) <= '0';
end if;
end if;
end process;

user_r_mem_32_empty <= '0';
user_r_mem_32_eof <= '0';
user_w_mem_32_full <= '0';
----------------------------------------------
My problems are:
-I can read and write from side b which is my own design, but when I write from Xillybus side(side a) using >memwrite \\.\xillybus_mem_32 0 ,it doesn't write.
-When I write ,for example "deadbeef" ,from side b and read it from side a using >memread \\.\xillybus_mem_32 0, the result value is "ef" . When I read the memory values from address 1,2 and 3; all of them are the same value as the address 0 which is "ef" which should be "be","ad" and "de" respectively.
- I used hexdump and I saw it reads memory values correctly.
How can I solve this problem?
Thanks for your help.
Arash
arash
 
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Re: Replacing mem with a dual port ram

Postby support »

Hello,

It's a bit unclear how you've set up your design, so I can only offer some general tips:

  • In order to use a 32-bit wide seekable interface, you need to define one at the IP Core Factory. The one in the demo bundle is 8 bit.
  • You'll also have to change memread and memwrite to read and write 32-bit words rather than 8 bit
  • Seeking takes place in multiples of 4. To access the word at address 3 on the FPGA, seek to (byte) position 12.

I hope one of these puts you back on track.

Eli
support
 
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Re: Replacing mem with a dual port ram

Postby Guest »

Hi Eli,
Thanks for your reply.
I have made my 32-bit wide interface at the IP Factory and used the 32-bit memwrite and read. I have used the same method to access to the word as you described.
If you look at the code that I sent you earlier, I have used a dual port ram instead of mem.
The dual port ram from one side (side A) is connected to the Xillybus, the same method as the mem is connected, and from another side (Side B) is connected to my core.
I can write and read data back from my core which is the side B of dual port ram.
From Side A which is the Xillybus side, when I use hexdump , I can access to the data I have written in the dual port ram by my core(side B). This means hexdump can read the memory data that I have written from side B correctly.
Consider I have written “deadbeef” in first address(address 0 inside of the memory). Hexdump can read this data but when I use >memread \\.\xillybus_mem_32 0, it gives me “ef”. Again , when I read address 1,2,and 3; it gives me “ef”. This means the hexdump value is not the same as memread.
As an example, When I use this command: >memwrite \\.\xillybus_mem_32 1 12345678, and read the data back, ( from address 4,5,6 and 7) , I can see the values are all zero. This menas the memwrite has not written in the memory.
The addressing should be correct as hexdump shows me the memory contains correctly. My designs met all of the constraints as well.
Thanks for your time
Arash
Guest
 

Re: Replacing mem with a dual port ram

Postby support »

Hello,

As I mentioned, memread and memwrite need to be updated to work with 32-bit words. This applies for the seeking steps as well as the amount of data to read.

It's no surprise that it doesn't work when attempting to read at positions 1, 2 and 3. These are illegal for 32-bit interfaces. Please take a look on these utilities.

Regards,
Eli
support
 
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Re: Replacing mem with a dual port ram

Postby mohdamir »

Hi Eli and everyone,

I use Xilinx Virtex 707 and ISE 14.7 for my design in my Windows, while my PCIe is x8 lane with 250MHz. I want to have Read/Write FIFO 32-bit, and a general purpose memory of 32-bit, same like this topic.

So, this is what I have done:

1) Generate a netlist using IP Core Factory:
xillybus_read_32, xillybus_write_32 (both 395 MB/s) which is General purpose
xillybus_mem_32 (102.400 kB/s) which is Address/data interface (5 address bits)

2) Replace the old netlist in core folder with the generated xillybus_core.ngc, and replace two files xillybus.v and xillybus_core.v in vhdl/src folder.

3) Modify the xillydemo by replacing with the generated template.

4) After restart the PC, I use two command prompt; one for memread \\.\xillybus_mem_32 4 and the other one is memwrite \\.\xillybus_mem_8 4 2882343476. (*Note that 2882343476 is decimal for ABCD1234 hex)

5) I read using memread xillybus_mem_32 at address 4, but the result is nothing, just 0. Iread at position 12, still 0. (*But my read/write 32-bit works really well)

Do you have any suggestion or idea, why I couldn't get the result?

Thanks alot.
mohdamir
 
Posts: 15
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Re: Replacing mem with a dual port ram

Postby support »

Hello,

To begin with, I remind you that you need to make some changes to memread and memwrite, so that they seek in 4-byte granularity and read/write 4 bytes for each operation. But this doesn't explain why you got zero as a result.

You said that you replaced xillydemo with the content of the instantiation template. I suppose that you also attached some logic implementing the registers or a synchronous memory...? Otherwise the wires to Xillybus remain "dangling", so nothing happens when you write, and it always reads zero. Which is what you got there.

Regards,
Eli
support
 
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