Using IP Cores with Xillybus Core

Questions and discussions about the Xillybus IP core and drivers

Using IP Cores with Xillybus Core

Postby Guest »

Dear Eli,

I have implemented a RGB to YCBCR converter using HLS with xillinux 1.3 on my Zedboard and would like to move on to something bigger. Rather than writing the entire image processing logic in HLS, I was wondering if it was possible to use existing IP Cores from the IP Catalog in Vivado (RGB to YCrCb Color-space Converter, Gamma Correction etc)?

After speaking to some of my professors, I understand that in order to use these IP Cores, AXI-4 stream must be supported.

Is it possible to use IP cores as our application logic and interface them with the fifos in xillybus? I have tried searching online and could not find discussion on this topic, and am starting to feel there is a reason why it is not feasible.
Guest
 

Re: Using IP Cores with Xillybus Core

Postby support »

Hello,

In order to connect an AXI stream to a FIFO, you'll need to write some (possible simple) glue logic between AXI to a plain stream of data. Since an AXI stream involves packeting of the data by virtue of the "last" signal, this issue needs to be handled per case.

For example, in many applications the packet length is constant, so the glue logic for sending data towards the host consists of just pushing the raw data into the FIFO, and let the program at the host divide the data into packets by knowing the length of each.

There is however no fit-all solution for converting an AXI stream into a FIFO stream, because of the extra meta-information that AXI supplies and requires.

Section 6.3 of Xillybus host application programming guide for Linux ("Packet communication") briefly discusses the issue of passing packets through Xillybus.

I hope this helped a bit.
Eli
support
 
Posts: 802
Joined:


Return to Xillybus