Using IP Cores with Xillybus Core
Posted:
Dear Eli,
I have implemented a RGB to YCBCR converter using HLS with xillinux 1.3 on my Zedboard and would like to move on to something bigger. Rather than writing the entire image processing logic in HLS, I was wondering if it was possible to use existing IP Cores from the IP Catalog in Vivado (RGB to YCrCb Color-space Converter, Gamma Correction etc)?
After speaking to some of my professors, I understand that in order to use these IP Cores, AXI-4 stream must be supported.
Is it possible to use IP cores as our application logic and interface them with the fifos in xillybus? I have tried searching online and could not find discussion on this topic, and am starting to feel there is a reason why it is not feasible.
I have implemented a RGB to YCBCR converter using HLS with xillinux 1.3 on my Zedboard and would like to move on to something bigger. Rather than writing the entire image processing logic in HLS, I was wondering if it was possible to use existing IP Cores from the IP Catalog in Vivado (RGB to YCrCb Color-space Converter, Gamma Correction etc)?
After speaking to some of my professors, I understand that in order to use these IP Cores, AXI-4 stream must be supported.
Is it possible to use IP cores as our application logic and interface them with the fifos in xillybus? I have tried searching online and could not find discussion on this topic, and am starting to feel there is a reason why it is not feasible.