Hi Eli and all,
I have implemented my own design using Xillybus for Virtex 707 board. My design consists of MicroBlaze system with computation logic and several FIFOs.
However, everytime I generate the bitstream, the timing constraint does not met. My attempt was by changing the placer cost table from one to another. And now it has been 40 since table 1, but it still does not met the timing.
Do you have any other suggestion? Thanks.
Xillybus VC707 timing constraint not met
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Re: Xillybus VC707 timing constraint not met
by support »
Hello,
Not meeting timing is often a fundamental design issue -- often a change in the design itself is required to fix it. The common term for fixing a problem like this is "timing closure". Xilinx has a lot of documentation on this topic. It has nothing to do with Xillybus specifically.
One thing to note is that Xillybus' user interface clock, bus_clk, runs at 250 MHz on Virtex-7 Xillybus bundles, which is quite high. Since the connection with Xillybus' IP core goes through FIFOs, it's possible to use dual-clock ("asynchronous") FIFOs, and run the application logic with any clock of choice. If the 250 MHz clock is an issue, this can help.
Regards,
Eli
Not meeting timing is often a fundamental design issue -- often a change in the design itself is required to fix it. The common term for fixing a problem like this is "timing closure". Xilinx has a lot of documentation on this topic. It has nothing to do with Xillybus specifically.
One thing to note is that Xillybus' user interface clock, bus_clk, runs at 250 MHz on Virtex-7 Xillybus bundles, which is quite high. Since the connection with Xillybus' IP core goes through FIFOs, it's possible to use dual-clock ("asynchronous") FIFOs, and run the application logic with any clock of choice. If the 250 MHz clock is an issue, this can help.
Regards,
Eli
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