Xillybus VC707 125MHz x4 Lane Width

Questions and discussions about the Xillybus IP core and drivers

Xillybus VC707 125MHz x4 Lane Width

Postby mohdamir »

Hi Eli and all,

I use Virtex-7 VC707, and by default the demo bundle use 250MHz with x8 lane width.

What I want to do is to reduce the clock to 125MHz with x4, so I uncomment pipe_lane[4] to pipe_lane[7] in *.ucf file for both TM_NET and LOC.

However, there is an error during translation process

Code: Select all
ConstraintSystem:58 - Constraint <NET "*/pipe_clock/pclk_sel" TIG;>[src/xillybus_vc707.ucf(45)]: NET "*/pipe_clock/pclk_sel" does not match any design objects.


I have no idea how to deal with this signal, pclk_sel basically.

Regards,
mohdamir
 
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Re: Xillybus VC707 125MHz x4 Lane Width

Postby support »

Hello,

Changing the lane width and bus frequency isn't trivial, and there's a lot of pitfalls in the process, which may lead to an unstable PCIe link. If your need is working with a clock that is slower than 250 MHz, I suggest interfacing with Xillybus through dual-clock ("asynchronous") FIFOs, so one side of the FIFO runs on the 250 MHz bus_clk and the second on any clock you choose for your application logic. This is much safer and simpler.

Regards,
Eli
support
 
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Re: Xillybus VC707 125MHz x4 Lane Width

Postby mohdamir »

Yup, that's what I've done this before, a dual asynchronous clock FIFO. From Xillybus it's 250 MHz while the other side it's my design which use 100 MHz.

But it seems that if for example I have 32kB of FIFO, and I try to send 64kB of data (in *.bin format) into one-go, some of the data is missing (there's no problem if I send a bit more data than original FIFO; for example 40kB of data).
Maybe it is due to the overlapping of fast writing over slow reading, in my opinion. So that's the reason why I think if I could slow down to 125 MHz while my application can increase up to 125 MHz to get the same frequency.

So in that case, I think I should send two times; by split the file into two chunks of 32kB (maybe?)

Thanks for your advice, Eli.
mohdamir
 
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Re: Xillybus VC707 125MHz x4 Lane Width

Postby support »

Hello,

There should be no data missing at all. If the FIFO's "full" port is connected to the Xillybus IP core as in the demo bundle's example, Xillybus will stop writing to the FIFO once it gets full, and resume writing when there's room again. So all data that was sent from the host will appear at the FIFO's read end, no matter how slow or fast it's read, or the size of the chunks it was written in. When properly connected, no data is lost, ever.

Attempting to slow down bus_clk would probably not solve the problem anyhow, by the way. I can see mainly three possibilities for your problem:

(1) The FIFO isn't connected properly to Xillybus' IP core (in particular, bus_clk to wr_clk and "full" to Xillybus' respective full signal)
(2) The logic loses the data while reading it (for example, rd_en tied high when data isn't accessed)
(3) The data wasn't written completely on the host. For example, write() may write less byte than the required by its call arguments. Always check its return value for how much data was actually written.

I hope this gave a direction.

Regards,
Eli
support
 
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Re: Xillybus VC707 125MHz x4 Lane Width

Postby mohdamir »

Oh I left the "full" port to open!

Thanks Eli for pointing me out.

Best regards
mohdamir
 
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