FIFO srst on !file open confusion

[Guest]

I see in the example verilog for the fifos that the srst terminal of the fifo often wired to the negation (!) of the file opened port of the xillybus module. I am confused how this works because fifos are supposed to store data while one side is transmitting it but the other side can't necessarily immediately consume the data when it is sent. If the fifo reset after the file is closed then wont all of the data that is queued it the fifo just be lost.

Basically, I have a stream of ~100 coefficients that I would like to stream to a scan chain. I want the host to be able to write to the device and be able to sent the ~100 coefficents. Once it is finished writing to the fifo I would like for the process to be able to move on to other things and not have to wait for the logic on the receiving side of the fifo to be finished consuming before it can close the file. Then at some later time I would like for it the host to write new coefficients and repeat the process again.

Am I missing something about srst and the open file wire? Should I hardcode the reset to 0? I don't understand why the xillybus documentation wires the reset to the whether the file is open because if my assumptions are correct it seems to obviate the purpose of the fifo which is that it stores inbound data until the consumer has a chance to use it.

[support]

Hello,

The *_open signal indicates that the file is open on the host side. So indeed, if the host program closes the file before the data is consumed on the FPGA, it is lost. In most applications, this doesn't happen, partly because the data is usually consumed way faster than the host's pace of doing things, but more importantly: There is usually no reason for the host to close the file until the entire saga is over.

So the point is: Open the file when the program starts, and close it before it exists. This allows the program to write some data, go on doing other things, and then write some more.

Only if you need the program to quit as soon as possible, let it wait for an indication that the FPGA is done (possibly through a Xillybus pipe in the other direction). The fact that the data has been sent doesn't drop the *_open signal -- only the closing of the file.

I hope this clarified the rationale.

Regards,
Eli