I want to create a device which reads the status from FPGA to host (my system will update the status of current operation to be read by host).
There are no synthesized error, however I got a mapping error, and attached below are the properties of my created device (from IP Core Factory) followed by the error (there are 64 errors which are almost similar). Could anyone point me what should I done? Thanks a lot.
Device name: xillybus_status_32
Direction: upstream (FPGA to host)
Data width: 32-bit
Expected bandwidth: 102.400 kB/s
Autoset: Yes
Details: Command and Status
- Code: Select all
LUT6 symbol
"xillybus_ins/xillybus_core_ins/wr_arbiter_ins/Mmux_wr_arb_state[2]_sendbuf_data[31]_wide_mux_45_OUT91" (output
signal=xillybus_ins/xillybus_core_ins/wr_arbiter_ins/wr_arb_state[2]_sendbuf_
data[31]_wide_mux_45_OUT[17]) has an equation that uses input pin I5, which
no longer has a connected signal. Please ensure that all the pins used in the
equation for this LUT have signals that are not trimmed (see Section 5 of the
Map Report File for details on which signals were trimmed).