DMA associated with xillybus_read_32

Questions and discussions about the Xillybus IP core and drivers

DMA associated with xillybus_read_32

Postby Guest »

I wanted to confirm that the default fifo's that come with the xillinux-eval-microzed-1-3b bundle have 4MB of DMA associated with them? I was assuming not, and went to make a custom core with larger DMA, but when I downloaded the original's from the core factory ( so I could see what their DMA setting was), it said 4MB. I was getting very slow times for my through put, and failures as data sent increased, so was just assuming the buffers were too small, but I would have thought 4MB was adequate.
Guest
 

Re: DMA associated with xillybus_read_32

Postby support »

Hello,

The DMA buffers of /dev/xillybus_read_32 and /dev/xillybus_write_32 have 32 MB each (in the demo bundle).

Either way, the size of these buffers have a rather minimal impact on throughput as well as latency, so it's not a surprise that your attempt to change their sizes made no difference.

It's not clear from your description how slow things went, and it what kind of failures you experienced, but these guidelines may come handy anyhow:
  • If you want to measure performance, please make sure that the buffer size allocated in the test program is at least 32 kB or so. With a 128-byte buffer, as shown in the demo applications, the CPU will be the bottleneck. You'll probably want to malloc() the buffer.
  • A loopback test isn't adequate, because the FIFO in the FPGA fills too quickly, which causes the flow to stall all the time. Either increase the FIFO's size considerably (say, 32 Kbytes) or modify the FPGA design so that the "empty" and "full" lines that go to the Xillybus IP core are never asserted (this will make the data garbled, as the FIFO will overfill and underrun without these signals).
  • Needless to say: For performance measurements, don't send or receive a file, as disk I/O is slow.
Regards,
Eli
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Re: DMA associated with xillybus_read_32

Postby Guest »

Thanks for your quick response. I'm loading a 13MB file into memory and "write"ing it to the fifo_write_32 in various chunk sizes (this is the buffer you're referring to I think). Sending each 23808 byte line works, but takes 6 sec. for 13MB, when I send two lines at a time, 47616 bytes, it continues to work and goes down to 3 sec. for the 13MB. Larger "chunks" sent result in varied, lesser than than sent, amounts being returned. The data are sent, split, swapped and run thru a simple algorithm, merged and returned, so its not just a loopback, but nothing that should take much time to process. I've tried both the forked processes example for the host program and running the read and write sequentially and get similar results.

Thinking the fifo was 32x512 as described in the docs, I had thought, in the core factory I would be able to define a larger fifo, but the settings only allow specifying the DMA buffers(?)
Where would I increase the fifo itself?
Guest
 

Re: DMA associated with xillybus_read_32

Postby support »

Hello,

The FPGA's internal FIFO of 32x512 is large enough. Making it bigger will not change anything, as the Xillybus IP core transports data soon enough to make the host's DMA memory space an extension of it.

The speeds you're reporting are way lower than Xillybus is capable of. Even though it's natural to blame something that you didn't write yourself, it's very unlikely that Xillybus is the bottleneck. As your own experience shows, fiddling with it hasn't made any difference.

I would suggest running "top" while your application is running. Is your process burning significant CPU time? Note that the CPU percentage next to each process is given related to a single processor's capability (it may exceed 100%), but the total statistics (idle time etc.) relates to both processors (100% means both processors are fully used).

Regards,
Eli
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