xillybus_read_32 is stalling for acquisition

Questions and discussions about the Xillybus IP core and drivers

xillybus_read_32 is stalling for acquisition

Postby Guest »

Hello, I am trying to connect an ADC board and ML605 with Xillybus. I basically copied over all of xillycapture.vhd, only changing two things:
- I got rid of the slowdown code
- I drove the capture clock with an external signal instead of bus_clk

Here is my code: http://pastebin.com/wsQga5YX . This is just the modified xillycapture.vhd. I added 4 ports to interface with the ADC firmware. I am pretty confident of the input of these ports, so I think the problem is in this code.
-in_data sends 32bit packets (equivalent of capture data)
-in_dval is asserted when the ADC is outputting data (usually after a trigger) (equivalent of capture_en)
-data_clock is synchronous with both in_data and in_dval. (equivalent of capture_clock)
-debug_button is currently not used

Furthermore, the async_fifo32 core is from the xillycapture download, and the xillybus_ins I downloaded from the IP core factory.

When I run the normal streamread/write on the 8bit FIFOs, everything works fine, so I know that the PCI connection is successful. However, I am interested in the 32bit FIFO. When I try to streamread, even during/after triggering ADC capture, I get nothing. I also tried to make it so that when I pressed the debug button, it inputs a stream of 1s into din and asserts wr_en to high. However, this also does nothing. If I try to call _read with any number of bytes, it hangs. So it seems no 32bit data is being written. Does anyone have an idea what is causing this?

Thanks,
Jon
Guest
 

Re: xillybus_read_32 is stalling for acquisition

Postby support »

Hello,

The fact that you get no data (read doesn't return) indicates that the Xillybus IP core sees an asserted 'empty' signal from the FIFO.

I can't see any evident problem, so I suggest trying this out:

Force the FIFO's wr_en = 1 and user_r_read_32_eof = 0. In this case, you should expect some data to flow.

Also (without the change above) try user_r_read_32_empty = 0 and user_r_read_32_eof = 0, and verify that something arrives to the PC (does the content give any hint?).

Are you sure that data_clock is active? Are you sure that in_dval is asserted?

Regards,
Eli
support
 
Posts: 802
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Re: xillybus_read_32 is stalling for acquisition

Postby Guest »

Hi again,

I tried setting wr_en to 1, eof to 0 and empty to 0 and it does change the output. However, I get some more unexpected behavior. Streamread no longer stalls, but prints out newlines indefinitely. Even if I set in_data to a constant value, it still prints newlines. Should I be getting the data I put in? i.e. if I make in_data = x"61616161" shouldn't I get a bunch of a's in my output? Perhaps I have the wrong understanding of it.

Furthermore, I also noticed that setting empty to 0 is what changes the behavior. If I connect the empty signal to the FIFO's empty port, it stalls once again.

Thanks,
Jon
Guest
 

Re: xillybus_read_32 is stalling for acquisition

Postby support »

Hello,

Guest wrote:Furthermore, I also noticed that setting empty to 0 is what changes the behavior. If I connect the empty signal to the FIFO's empty port, it stalls once again.


This is a strong indication that no data is fed into the FIFO. That the FIFO's wr_en remains deasserted, or that its reset is asserted. Your FIFO remains empty, so no data is read from it.

Guest wrote:i.e. if I make in_data = x"61616161" shouldn't I get a bunch of a's in my output?


Well, in_data is the input to the FIFO, and wr_en is never asserted, so it doesn't really matter what in_data is. So you get the default value at the FIFO's output (all read attempts fail, as the FIFO is empty) which is probably all zeros. But if you set user_r_read_32_data to that value, you should see a change.

Regards,
Eli
support
 
Posts: 802
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