Hello, I am trying to connect an ADC board and ML605 with Xillybus. I basically copied over all of xillycapture.vhd, only changing two things:
- I got rid of the slowdown code
- I drove the capture clock with an external signal instead of bus_clk
Here is my code: http://pastebin.com/wsQga5YX . This is just the modified xillycapture.vhd. I added 4 ports to interface with the ADC firmware. I am pretty confident of the input of these ports, so I think the problem is in this code.
-in_data sends 32bit packets (equivalent of capture data)
-in_dval is asserted when the ADC is outputting data (usually after a trigger) (equivalent of capture_en)
-data_clock is synchronous with both in_data and in_dval. (equivalent of capture_clock)
-debug_button is currently not used
Furthermore, the async_fifo32 core is from the xillycapture download, and the xillybus_ins I downloaded from the IP core factory.
When I run the normal streamread/write on the 8bit FIFOs, everything works fine, so I know that the PCI connection is successful. However, I am interested in the 32bit FIFO. When I try to streamread, even during/after triggering ADC capture, I get nothing. I also tried to make it so that when I pressed the debug button, it inputs a stream of 1s into din and asserts wr_en to high. However, this also does nothing. If I try to call _read with any number of bytes, it hangs. So it seems no 32bit data is being written. Does anyone have an idea what is causing this?
Thanks,
Jon