Program to output a static value

[openmpi]

Hello. I writing this program in order to understand better how Xillybus works. Starting from xillydemo.vhd, I want that the program prints out the value "01010101" whatever the user type as input in ./streamwrite /dev/xillybus_write_8. For example, if the user writes "hello" after executing ./streamwrite /dev/xillybus_write_8, on the other terminal in which ./streamread /dev/xillybus_read_8 is running, it has to appear "01010101" instead of "hello". What I have done, is to modify this piece of code of xillydemo.vhd:

Code: Select all

begin
    user_w_mem_8_data <= "01010101";
   
    if (bus_clk'event and bus_clk = '1') then
      if (user_w_mem_8_wren = '1') then
       demoarray(ram_addr) <= user_w_mem_8_data;
      end if;
      if (user_r_mem_8_rden = '1') then
        user_r_mem_8_data <= demoarray(ram_addr);
      end if;
    end if;
  end process;


As you can see, I have added on top of the code the line user_w_mem_8_data <= "01010101"; to force the data to be written in the memory. Unfortunately this method does not work. Any suggestion?

Thanks

[support]

Hello,

As a general remark, let me advise you to supply more information when something doesn't work. Like what you expected to happen, and what actually happened.

In your case there are two reasons I can see why you didn't get what you expected. To begin with, you're altering the wrong variable: user_w_mem_8_data belongs to /dev/xillybus_mem_8. You want to play with user_w_read_8, I suppose.

Another thing is the formats of your literal. I believe that you wanted the output of the string 01010101, and not the binary representation of it. You can't just feed a string like that. You'll have to assign each byte, probably as a number, each on the clock cycle it belongs to. You'll need to set up a small state machine for that, most likely.

I suggest taking the time to understand how the existing example works before trying to hack it. It's not always as obvious as it may seem.

Regards,
Eli

[openmpi]

Hi Eli, thanks for your suggestion. By editing the code in this way, I almost got what I wanted.

Code: Select all

begin
    if (bus_clk'event and bus_clk = '1') then
      if (user_w_mem_8_wren = '1') then
        demoarray(ram_addr) <= user_w_mem_8_data;
      end if;
      if (user_r_mem_8_rden = '1') then
        user_r_mem_8_data <= demoarray(ram_addr);
        user_r_read_8_data <= "01010100"; --T
      end if;
    end if;
  end process;

In this way, whatever the user types in ./streamwrite /dev/xillybus_write_8, in the terminal in which ./streamread /dev/xillybus_read_8 is running, xillybus will always print T.

As next step, I want to read what the user types in ./streamwrite /dev/xillybus_write_8, increment the value typed of 1 and print out as I did above. For example, if the user types T (that in binary corresponds to 01010100), the program must add 1 to 01010100 and print out in this case U (because 01010100+00000001=01010101). This is what I did:

Code: Select all

begin
   tmp <= "00000001";
    if (bus_clk'event and bus_clk = '1') then
      if (user_w_mem_8_wren = '1') then
        demoarray(ram_addr) <= user_w_mem_8_data;
      end if;
      if (user_r_mem_8_rden = '1') then
        user_r_mem_8_data <= demoarray(ram_addr);
        user_r_read_8_data <= std_logic_vector(unsigned(user_w_write_8_data) + unsigned(tmp));
      end if;
    end if;
  end process;


As you can see, it sums user_w_write_8_data and tmp. Unfortunately, Vivado does not generate the bitstream because of the addition. My question is: does user_w_write_8_data contains the value typed by the user in ./streamwrite /dev/xillybus_write_8? Sorry but I did not find it in the documentation.

Thanks.

[openmpi]

I think I get error because user_w_write_8_data is defined as OUT and Xillybus fpga api doc, says that user_w_{devfile}_data contains data during write cycles. Thus, who contains the value typed by the user? It should be stored in some std_logic_vector but I do not understand which one it is.

[support]

Hello,

It looks like you're making your first steps in VHDL programming -- welcome aboard.

However this forum focuses on issues related to Xillybus directly. It might be more easy if you sought help in VHDL-related forums, possibly on Xilinx' or Altera's web sites.

Looking at your code, I see that you assign a value to user_r_read_8_data when user_r_mem_8_rden is asserted. So in theory, there would be a need to read from mem_8's stream to have the data assigned (in the first code example) or have it incremented (on the second example).

The reason you got a 'T' at all previously is either that you tried to read something from mem_8 while experimenting, or that the synthesizer chose the desired value as the initial startup value, because it's the only value it's assigned. This is a common optimization.

Regards,
Eli

[openmpi]

What do you mean by read from mem_8's stream? Which of the mem_8 signals? Thanks.

[support]

Hi,

I actually meant that the host performs a read() call from mem_8. But never mind that. It was just an attempt to explain why the current situation was wrong.

Regards,
Eli