Hi Eli, thanks for your suggestion. By editing the code in this way, I almost got what I wanted.
- Code: Select all
begin
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
user_r_read_8_data <= "01010100"; --T
end if;
end if;
end process;
In this way, whatever the user types in
./streamwrite /dev/xillybus_write_8, in the terminal in which
./streamread /dev/xillybus_read_8 is running, xillybus will always print T.
As next step, I want to read what the user types in
./streamwrite /dev/xillybus_write_8, increment the value typed of 1 and print out as I did above. For example, if the user types T (that in binary corresponds to 01010100), the program must add 1 to 01010100 and print out in this case U (because 01010100+00000001=01010101). This is what I did:
- Code: Select all
begin
tmp <= "00000001";
if (bus_clk'event and bus_clk = '1') then
if (user_w_mem_8_wren = '1') then
demoarray(ram_addr) <= user_w_mem_8_data;
end if;
if (user_r_mem_8_rden = '1') then
user_r_mem_8_data <= demoarray(ram_addr);
user_r_read_8_data <= std_logic_vector(unsigned(user_w_write_8_data) + unsigned(tmp));
end if;
end if;
end process;
As you can see, it sums user_w_write_8_data and tmp. Unfortunately, Vivado does not generate the bitstream because of the addition. My question is: does user_w_write_8_data contains the value typed by the user in
./streamwrite /dev/xillybus_write_8? Sorry but I did not find it in the documentation.
Thanks.