Hi Eli,
I am using Xillinux 1.3 with Vivado 2014.1 and ZedBoard. I used your IP factory to create a new upstream of 345MB/s and a new downstream of 345MB/s. After I downloaded the customized core bundle from the IP factory, I replaced the old xillybus.v, xillybus_core.v, and xillybus_core.ngc with the new ones from the bundle. Then I edited my xillydemo.v according to the template.v provided by the core bundle.
However, the instantiation of the xillybus module in template.v contains a part (line 174 to line 201) shown below:
// General signals
.PS_CLK(PS_CLK),
.PS_PORB(PS_PORB),
.PS_SRSTB(PS_SRSTB),
.clk_100(clk_100),
.otg_oc(otg_oc),
.DDR_Addr(DDR_Addr),
.DDR_BankAddr(DDR_BankAddr),
.DDR_CAS_n(DDR_CAS_n),
.DDR_CKE(DDR_CKE),
.DDR_CS_n(DDR_CS_n),
.DDR_Clk(DDR_Clk),
.DDR_Clk_n(DDR_Clk_n),
.DDR_DM(DDR_DM),
.DDR_DQ(DDR_DQ),
.DDR_DQS(DDR_DQS),
.DDR_DQS_n(DDR_DQS_n),
.DDR_DRSTB(DDR_DRSTB),
.DDR_ODT(DDR_ODT),
.DDR_RAS_n(DDR_RAS_n),
.DDR_VRN(DDR_VRN),
.DDR_VRP(DDR_VRP),
.MIO(MIO),
.PS_GPIO(PS_GPIO),
.DDR_WEB(DDR_WEB),
.GPIO_LED(GPIO_LED),
.bus_clk(bus_clk),
.quiesce(quiesce)
Most signals (especailly those staring with "DDR") above cannot be found in the xillydemo.v. This issue prevented me from using the customized XIllybus IP in my project. Could you clarify this problem
please?
Any response would be appreciated. Thank you!