transplant an ISE project into a vivado one

Questions and discussions about the Xillybus IP core and drivers

transplant an ISE project into a vivado one

Postby Guest »

Hello guys,
currently I have an ISE project containing xillybus modules and for some reasons I need to change it into a vivado project
The project is for vc707 and I've tried to modified it according to the xillydemo downloaded from here http://xillybus.com/pcie-download

The first problem is,
I have added all the things in the vivado-essentials folder and found a module named "pcie_k7_vivado_pipe_clock" missing, I have no idea where should the file be.

And for the other,
Now I have tried to use the verilog files generated from ISE IP instead of the vivado IP in the vivado-essentials, during the synthesize process came out some critical warnings stated that the "minireport" in .tcl file I added from vivado-essentials could not works.
[Designutils 20-964] Command failed: can't read "minireport": no such variable.
I know the commands in this .tcl are simply for timing check but I still don't know why the file in vivado-essentials doesn't work in vivado.


The last problem came after I removed the .tcl file from the project.
The top-module contained some xillybus IO ports like
input PCIE_PERST_B_LS,
input PCIE_REFCLK_N,
input PCIE_REFCLK_P,
input [7:0] PCIE_RX_N,
input [7:0] PCIE_RX_P,
output [7:0] PCIE_TX_N,
output [7:0] PCIE_TX_P,
when I finally finished the synthesizing and implementing process and tried to generate bitstream, it bumped out errors stating that the user define IOs should always be assigned location and some of them was not assigned. I have never met such an errors in ISE environment. The constrain file for xillybus in the project now is just the .xdc file from vivado-essentials, so how can I solve the error?
In the error message showed a command to skip it over but I am just wonder whether it would make something wrong?

thanks for answering my question, I am not quite familiar to vivado yet and your answer do help me a lot!
Guest
 

Re: transplant an ISE project into a vivado one

Postby support »

Hi,

Even though there's a wizard for importing ISE projects in Vivado, I would recommend starting off from a clean Xillydemo project going through the Vivado flow, and verify that you get that up and running. Then modify the project to adjust it with the changes you made in the ISE project. Add your sources into the src/ directory (or where you find sensible) and add them to the project in Vivado's GUI.

Translate your constraints to a new XDC file. Pin placements and timing.

If you have any Xilinx IP cores, redefine them in Vivado's GUI from scratch. In theory, Vivado can import XCO files, but sometimes this or other parameter gets wrong, and then go figure why it doesn't work.

Either way, I don't think you have anything particular to do in the vivado-essentials directory.

Vivado doesn't like when the user tampers with its files. ISE is fairly tolerant in this respect.

So even though it's somewhat tedious to rebuild the project, it's probably the shortest path. Trying to figure out why Vivado isn't happy is much harder.

A final note: You may want to look at this after you get it all together, in order to have some control on which file does what: http://xillybus.com/tutorials/vivado-ve ... -packaging

Regards,
Eli
support
 
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