Hi Eli!
Sorry for the mistake, I meant transferring data from local machine to xillybus_write_8 (not to xillybus_read).
What I want to do is to pass an input file that contains words from my local machine to FPGA, process words by increasing all single characters of 1, and write the result on an output text file.
E.g., if the input file contains the word "hello", the output file file must contain the string "ifmmp". (because of h+1=i, e+1=f, l+1=m, l+1=m, o+1=p)
More precisely, what I want to do is to:
1. copy data from input text file (dictionary text file) to xillybus_write_8.
2. process data on FPGA by increasing of 1 all the characters of the input file.
3. generate an output file with all characters increased of 1.
This is my Java code:
the inputPath contains the path of the Engish dictionary text file and outputPath contains the path in which I want to store the output file (data processed by FPGA). In the first while loop I copy the input file (dictionary) on xillybus_write_8. The problem is that my application gets stuck in this loop while. The second while loop, copies the data from xillybus_read_8 (in which there is the strings already increased by the VHDL program) to output.txt
- Code: Select all
import java.io.File;
import java.io.FileInputStream;
import java.io.FileNotFoundException;
import java.io.FileOutputStream;
import java.io.IOException;
import java.io.InputStream;
import java.io.OutputStream;
public class PutGet_8_main {
public static void main(String [] args) {
try {
String inputPath = args[0];
String outputPath = "/home/paolo/final_fpga/test_put_get/output.txt";
String tmp = new String ("");
//Initialize Put
File f1Put = new File(inputPath);
File f2Put = new File("/dev/xillybus_write_8");
InputStream inPut = new FileInputStream(f1Put);
OutputStream outPut = new FileOutputStream(f2Put, true);
byte[] bufPut = new byte[1024];
int lenPut;
//Initialize Get
File f1Get = new File("/dev/xillybus_read_8");
File f2Get = new File(outputPath);
InputStream inGet = new FileInputStream(f1Get);
OutputStream outGet = new FileOutputStream(f2Get, true);
byte[] bufGet = new byte[1024];
int lenGet;
//Write on xillybus_write_8
System.out.println("Before putting");
while ((lenPut = inPut.read(bufPut)) > 0) {
//tmp = new String (bufPut);
//System.out.println("Putting: " + tmp);
outPut.write(bufPut, 0, lenPut);
}
System.out.println("After putting");
inPut.close();
outPut.close();
//Read from xillybus_read_8
System.out.println("Before getting");
while ((lenGet = inGet.read(bufGet)) > 0) {
//tmp = new String (bufGet);
//System.out.println("Getting: " + tmp);
outGet.write(bufGet, 0, lenGet);
}
System.out.println("After getting");
inGet.close();
outGet.close();
}
catch (FileNotFoundException ex) {
System.out.println(ex.getMessage() + " in this directory.");
System.exit(0);
}
catch (IOException e) {
System.out.println(e.getMessage());
}
}
}
This is the VHDL code:
Basically, I get the data from user_w_write_8_data, I increase it of 1 (user_w_write_8_data+1) and finally I store it in din.
- Code: Select all
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity xillydemo is
port (
PCIE_PERST_B_LS : IN std_logic;
PCIE_REFCLK_N : IN std_logic;
PCIE_REFCLK_P : IN std_logic;
PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0));
end xillydemo;
architecture sample_arch of xillydemo is
signal tmp : std_logic_vector(7 DOWNTO 0);
component xillybus
port (
PCIE_PERST_B_LS : IN std_logic;
PCIE_REFCLK_N : IN std_logic;
PCIE_REFCLK_P : IN std_logic;
PCIE_RX_N : IN std_logic_vector(3 DOWNTO 0);
PCIE_RX_P : IN std_logic_vector(3 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0);
PCIE_TX_N : OUT std_logic_vector(3 DOWNTO 0);
PCIE_TX_P : OUT std_logic_vector(3 DOWNTO 0);
bus_clk : OUT std_logic;
quiesce : OUT std_logic;
user_r_read_8_rden : OUT std_logic;
user_r_read_8_empty : IN std_logic;
user_r_read_8_data : IN std_logic_vector(7 DOWNTO 0);
user_r_read_8_eof : IN std_logic;
user_r_read_8_open : OUT std_logic;
user_w_write_8_wren : OUT std_logic;
user_w_write_8_full : IN std_logic;
user_w_write_8_data : OUT std_logic_vector(7 DOWNTO 0);
user_w_write_8_open : OUT std_logic);
end component;
component fifo_8x2048
port (
clk: IN std_logic;
srst: IN std_logic;
din: IN std_logic_VECTOR(7 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of fifo_8x2048: component is true;
signal bus_clk : std_logic;
signal quiesce : std_logic;
signal reset_8 : std_logic;
signal ram_addr : integer range 0 to 31;
signal user_r_read_8_rden : std_logic;
signal user_r_read_8_empty : std_logic;
signal user_r_read_8_data : std_logic_vector(7 DOWNTO 0);
signal user_r_read_8_eof : std_logic;
signal user_r_read_8_open : std_logic;
signal user_w_write_8_wren : std_logic;
signal user_w_write_8_full : std_logic;
signal user_w_write_8_data : std_logic_vector(7 DOWNTO 0);
signal user_w_write_8_open : std_logic;
signal wr_en : std_logic := '0';
signal din : std_logic_vector(user_w_write_8_data'range) := (others => '0');
begin
xillybus_ins : xillybus
port map (
-- Ports related to /dev/xillybus_read_8
-- FPGA to CPU signals:
user_r_read_8_rden => user_r_read_8_rden,
user_r_read_8_empty => user_r_read_8_empty,
user_r_read_8_data => user_r_read_8_data,
user_r_read_8_eof => user_r_read_8_eof,
user_r_read_8_open => user_r_read_8_open,
-- Ports related to /dev/xillybus_write_8
-- CPU to FPGA signals:
user_w_write_8_wren => user_w_write_8_wren,
user_w_write_8_full => user_w_write_8_full,
user_w_write_8_data => user_w_write_8_data,
user_w_write_8_open => user_w_write_8_open,
-- General signals
PCIE_PERST_B_LS => PCIE_PERST_B_LS,
PCIE_REFCLK_N => PCIE_REFCLK_N,
PCIE_REFCLK_P => PCIE_REFCLK_P,
PCIE_RX_N => PCIE_RX_N,
PCIE_RX_P => PCIE_RX_P,
GPIO_LED => GPIO_LED,
PCIE_TX_N => PCIE_TX_N,
PCIE_TX_P => PCIE_TX_P,
bus_clk => bus_clk,
quiesce => quiesce
);
process (bus_clk)
begin
if (bus_clk'event and bus_clk = '1') then
wr_en <= user_w_write_8_wren;
if (user_w_write_8_wren = '1') then
din <= user_w_write_8_data+1;
end if;
end if;
end process;
-- 8-bit loopback
fifo_8 : fifo_8x2048
port map(
clk => bus_clk,
srst => reset_8,
din => din,
wr_en => wr_en,
rd_en => user_r_read_8_rden,
dout => user_r_read_8_data,
full => user_w_write_8_full,
empty => user_r_read_8_empty
);
reset_8 <= not (user_w_write_8_open or user_r_read_8_open);
user_r_read_8_eof <= '0';
end sample_arch;
If I execute this application with small input file, it generates the output file with all characters increased of 1. The problem is that I have an input file with many words such as an english dictionary. With big file the application gets stuck when it copies the input file to write_device_file. Is it clear now?
Thanks