Serial to Parallel Data Stream

[Guest]

Dear Eli,

In my application, I have a continuous data source which contains multichannel of data sample. So after the data flow out of FIFO, I need to put the first sample of data into a filter and second sample of data into another filter and so on and so forth, there might be 512 channels. It is a general serial to parallel operation.

So I am trying to customize the `xiilycapture.v` to realize that. But I don't have a general idea about how to hack the data-flow to realize it.

Do I need a counter in the asyn FIFO and a shift register and state machine after the FIFO? If that is the case, how do I add counter in the FIFO you provide?

Best,
Chongxi

[support]

Hello,

Had it not been up 512 channels, but something like 16 or so, I would have suggested assigning separate Xillybus streams for each filter.

In your case, it seems like you need to implement a demultiplexer (demux for short). it doesn't make much sense to try changing the FIFO connected to the Xillybus core. Rather, the application logic should read data from the FIFO, and pass it on to each of the filters in a round robin manner. So yes, there is a counter (which I would zero when the *_open signal is low), but it keeps track on which of the filters should get the data next.

My description is rather vague, because what to implement depends on how the filters expect to receive the data. Googling for "demux" along with "Verilog" or "VHDL" or "FPGA" or something similar will probably bring you to some helpful examples.

Regards,
Eli

[Guest]

Thanks very much for your helpful and quick reply!

It seems demux is exactly the thing what I need now. I need to use the clock signal to demux the incoming data stream.

Could you please tell me which signal is this data sample clock I can use to demux? Is it the capture_clk in the below Verilog code?

async_fifo_32 fifo_32
(
.rst(!user_r_read_32_open),
.wr_clk(capture_clk),
.rd_clk(bus_clk),
.din(capture_data),
.wr_en(capture_en),
.rd_en(user_r_read_32_rden),
.dout(user_r_read_32_data),
.full(capture_full),
.empty(user_r_read_32_empty)
);

Thank you very much!

Best,
Chongxi

[Guest]

By reading from the FIFO, do you mean the data flow below?


----> filter 0
----> filter 1
data source ---> FIFO_1 ----> demux ----> filter 2 ---> mux ---> FIFO_2 ---> xillybus IP
----> filter 3
----> filter 4
...

So I need 2 FIFOs?

Best,
Chongxi

[support]

Hello,

You asked two questions: First, which clock to use. That depends. You may use a dual-clock ("asynchronous") FIFOs and let your logic run on a clock other than bus_clk, or use single-clock ("synchronous") FIFOs and then use bus_clk for the logic.

And yes, if you want to send data for processing to the FPGA in one stream and get back the processed data in another, you need a FIFO for each, so two of them.

I really suggest making yourself acquainted with standard FIFOs a bit. It's a common and useful technique in FPGA design, and it's really something that you need sorted out when working with Xillybus.

Regards,
Eli