Dear Eli,
In my application, I have a continuous data source which contains multichannel of data sample. So after the data flow out of FIFO, I need to put the first sample of data into a filter and second sample of data into another filter and so on and so forth, there might be 512 channels. It is a general serial to parallel operation.
So I am trying to customize the `xiilycapture.v` to realize that. But I don't have a general idea about how to hack the data-flow to realize it.
Do I need a counter in the asyn FIFO and a shift register and state machine after the FIFO? If that is the case, how do I add counter in the FIFO you provide?
Best,
Chongxi