Xillybus FIFO connect with AXI4-stream interface

Questions and discussions about the Xillybus IP core and drivers

Xillybus FIFO connect with AXI4-stream interface

Postby Guest »

Hi Eli,

I've been playing around Xillybus for a while and all of my questions had been perfectly addressed.

I want to thank you and this is really a good IP that everyone should use.

I have another question that nowadays a lot of IP seems to use AXI4-stream interface while the FIFO provided in the xillydemo is still using conventional interface.

What should be done to change the provided FIFO into a AXI4-stream based FIFO, do I need to customize the xillybus core for that purpose?

Best,
Chongxi
Guest
 

Re: Xillybus FIFO connect with AXI4-stream interface

Postby support »

Hello,

Let's start with what won't make any difference: A custom IP core. All IP cores you can create in the IP Core Factory have the same FIFO interface.

The first thing to realize when interfacing a AXI4-stream with a plain FIFO is that the AXI4-stream interface actually sends and receives packets, which are separated using the AXI4's LAST signal. FIFOs have no such feature. The Programming guides for both Linux and WIndows (which are available at Xillybus' site) have a short section on how to transmit packets conveniently through Xillybus streams, so I'll leave that aside.

If the AXI4 stream doesn't use the LAST signal (i.e. the data is continuous) it's quite simple to connect it to a FIFO. For communication with Xillybus, a FIFO should be connected to the Xillybus IP core on one side, and to the AXI4 stream on the other, as follows. First, the data ports should be connected to each other, that's quite obvious.

As for the control signals. If the AXI4 feeds the FIFO with data: Connect (combinatorically) wr_en = (VALID & READY), READY = !full.

For the other direction, FIFO feeding AXI4, it's easiest to use a FWFT FIFO (or "fake" one, see http://www.billauer.co.il/reg_fifo.html) and connect (combinatorically) VALID = !empty, rd_en = (VALID & READY). The FWFT (First Word Fall Through) FIFO's empty signal is deasserted when there is already a valid word on the data port, and hence this simple connection.

But again, all this makes sense if the LAST signal is outside the game. If it is, some application dependent adjustments are required.

Regards,
Eli
support
 
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Re: Xillybus FIFO connect with AXI4-stream interface

Postby Guest »

Hi Eli,

That could not be clearer. Thank you very much.

BTW, I just realize that you are the Eli! I have been used your `peakdet` all the time! Amazing!

Best,
Chongxi
Guest
 


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