Hello,
Let's start with what
won't make any difference: A custom IP core. All IP cores you can create in the IP Core Factory have the same FIFO interface.
The first thing to realize when interfacing a AXI4-stream with a plain FIFO is that the AXI4-stream interface actually sends and receives packets, which are separated using the AXI4's LAST signal. FIFOs have no such feature. The Programming guides for both Linux and WIndows (which are available at Xillybus' site) have a short section on how to transmit packets conveniently through Xillybus streams, so I'll leave that aside.
If the AXI4 stream doesn't use the LAST signal (i.e. the data is continuous) it's quite simple to connect it to a FIFO. For communication with Xillybus, a FIFO should be connected to the Xillybus IP core on one side, and to the AXI4 stream on the other, as follows. First, the data ports should be connected to each other, that's quite obvious.
As for the control signals. If the AXI4 feeds the FIFO with data: Connect (combinatorically) wr_en = (VALID & READY), READY = !full.
For the other direction, FIFO feeding AXI4, it's easiest to use a FWFT FIFO (or "fake" one, see
http://www.billauer.co.il/reg_fifo.html) and connect (combinatorically) VALID = !empty, rd_en = (VALID & READY). The FWFT (First Word Fall Through) FIFO's empty signal is deasserted when there is already a valid word on the data port, and hence this simple connection.
But again, all this makes sense if the LAST signal is outside the game. If it is, some application dependent adjustments are required.
Regards,
Eli