Hello,
i am a bit confused about the relation between the data width of a stream to the buffer type used in a write() or read() operation. For example suppose that i have a 32bit wide host to fpga stream and in my program i defined a buffer variable as
unsigned char my_buffer[128]. After assigning values to the buffer and call write(fd,my_buffer,sizeof(my_buffer)) the data go to a DMA buffer. How does Xillybus transmit the data to my logic? Does it transmit each my_buffer[i] adding zeros in front to match 32bit width