Write 16bits width data instead of 32 bits

[Guest]

Hi eli,

As I asked in the previous questions. I tried to connect two FIFO together and put a multichannel-FIR between two FIFOs. It works based on your answers! I received the filtered data of multiple channels data that I download into FPGA through xillybus. Thank you!

However, there is still a little bug. My downloaded data is 16bits width and after FIR it becomes 32bits. There is no problem on the reading side, but on the writing side, I still use your 32 bits FIFO and just feed 0-15bits to the FIR module. ( assign fir_in = fifo0_dout[15:0]; )

I thought since my downloaded data is 16bits wide, the w32 steam would pad zeros in the MSB 16bits. But it seems does not work in that way. That actually make me lose half of the data samples which I don't intend to. So what should I do, should I change the FIFO before FIR into a 16bits width FIFO?

Thanks!

Best,
Chongxi

[support]

Hello,

I don't know if this is the question you asked, but the issue is discussed on this thread:

viewtopic.php?f=4&t=387

I can see two possible solutions for your situation:

1. Send an array of int or unsigned int (32-bit words) to the stream, with values are small enough to fit 16 bits. This way the host pads the zeros. This is a waste of transmission bandwidth, but if it's fast enough anyhow, it's a quick solution.

2. Use an asymmetric FIFO on the FPGA, with an input of 32 bits and output of 16 bits. This is a possible configuration in Xilinx' core generator. The data will get organized properly this way.

Regards,
Eli

[Guest]

Hi, eli,

Your first solution works very well. I just tried, now the whole system works perfectly except that the channel sequence change from [ch0,ch1,ch2,...ch15] to [ch1,ch2,ch3,...ch15,ch0], each channel sample data is int32 now. Probably is the problem of FWFT-FIFO? But at least, the multichannel FIR filter works very well with two FIFO through AXI4 stream! The total quantization error between FPGA filter and MATLAB filter is less than 1e-5, but FPGA is massively parallel.

I have a further question. For my project, it is going to collect external data stream instead of downloading data from HOST to FPGA, and the external data stream is indeed 16 bits wide with multichannel interleaved. Do I need to change the first FIFO data width to 16bits-in and 16-bits out in that case?

Best,
Chongxi

[support]

Hello,

Yes, indeed, it sounds like you have some kind data synchronization issue with the FIR's input. This is a common headache with FPGA design: Getting the data in the right place at the right time.

As for FIFOs from external input to the FIRs, that pretty much depends on the setting. For example, if the FIR data arrives at the clock rate that drives the FIR, there's no need for a FIFO at all -- just connect the data directly and hold the AXI "valid" line high all the time.

In other cases, you might benefit from an asymmetric FIFO for the task of diving the interleaved data, and feed e.g. two 16-bit FIRs with two halves of a 32-bit word each.

Or, you may generate a custom IP core at the IP Core Factory at the site, so that these data streams are completely independent. It depends on what you want to achieve.

Regards,
Eli

[Guest]

Hi eli,

Thanks again! It is very helpful talking to you as always.

It seems this is a real problem for me. That it is critical to know which data stream is from which channel. However everytime I collect data from PCIE the sequence might be wrong. Should I add some verify logic to the data stream itself? or there is another way to do that? Sorry, this is sort of off-topic question but I really don't know how to cope with.

Best,
Chongxi

[support]

Hi,

The recommended way to synchronize the logic that receives the data is to bring it to a known state (i.e. reset it) when the Xillybus *_open line goes low. This ensures a repeatable reception of the data.

Regards,
Eli

[Guest]

I see. When I r32.close(), the 'r_open' signal is active low and the read FIFO is reset.

Thanks eli!

Best,
Chongxi