The behavior of FIFO rd_en

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The behavior of FIFO rd_en

Postby Guest »

Hi Eli,

As in the previous post, you suggested me how to connect two FIFOs (one FWFT and one regular) and a FIR based on AXI4 stream between these 2 FIFOs.

With that structure, fifo_32_1 receive data from FIR and send data to Xillybus.

fifo_32x512 fifo_32_1
(
.clk(bus_clk),
.srst(!user_r_read_32_open),
.din(tohost),
.wr_en(fir_valid && !fifo1_full), // AXI4 valid and ready
.rd_en(user_r_read_32_rden), // FPGA to CPU
.dout(user_r_read_32_data),
.full(fifo1_full),
.empty(user_r_read_32_empty)
);

Here is a debug data captured by Vivado ILA, which shows the fifo_32_1/din[31:0] captured when fifo_32_1_rd_en asserted.
Image
https://raw.githubusercontent.com/chongxi/KC705_PCIE/master/clock.PNG

It seems that fifo_32_1_rd_en signal is asserted not as regular as fifo_32_1_wr_en.
I understand this rd_en is controlled by the host (user_r_read_32_rden). It seems that some of rd_en signal is longer than others and it does not come with a regular interval. Would this cause any data missing or loss?

Best,
Chongxi
Guest
 

Re: The behavior of FIFO rd_en

Postby support »

Hello,

There is no specific pattern that user_r_read_32_rden should have, so I see no problem. If it looks uneven in the logic analyzer capture, so be it. The whole point with putting a FIFO in the middle is to decouple the data fetching from its generation.

Regards,
Eli
support
 
Posts: 802
Joined:

Re: The behavior of FIFO rd_en

Postby Guest »

Yes, you are absolutely right. This is a stupid question.

It is the rd_en that exposes the data in memory to the Dout of FIFO, so the rd_en does not have to be regular timed...

Best,
Chongxi
Guest
 


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