Default bus_clk frequency on Zybo

Questions and discussions about the Xillybus IP core and drivers

Default bus_clk frequency on Zybo

Postby pichldom »

Hello,
I'm using xillybus on Zybo to transfer data from Linux host to FPGA (with and without FIFO) and I need to know the default frequency of bus_clk clock, because I also need to generate other clocks with specific frequencies. I tried to search for it and found different answers (70MHz and 100MHz). Does anyone know the right answer?

Thank you in advance.
Dominika
pichldom
 
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Re: Default bus_clk frequency on Zybo

Postby support »

Hello,

It's not clear where the 70 MHz figure came from. Anyhow, the bus_clk is another name for the clock called clk_fpga_1 by Vivado. From the timing report of xillinux-eval-zybo-1.3c's demo bundle's implementation on Vivado, we have (the file is xillydemo_timing_summary_routed.rpt)

Code: Select all
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock                  Waveform(ns)         Period(ns)      Frequency(MHz)
-----                  ------------         ----------      --------------
clk_fpga_1             {0.000 5.000}        10.000          100.000         
gclk                   {0.000 4.000}        8.000           125.000         
  audio_mclk_OBUF      {0.000 41.667}       83.333          12.000         
  clk_fb               {0.000 20.000}       40.000          25.000         
  vga_clk_ins/clk_fb   {0.000 20.000}       40.000          25.000         
  vga_clk_ins/clkout0  {0.000 1.538}        3.077           325.000         
  vga_clk_ins/clkout1  {0.000 7.692}        15.385          65.000         
  vga_clk_ins/clkout2  {0.000 7.692}        15.385          65.000         


So the answer is 100 MHz.

Regards,
Eli
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Re: Default bus_clk frequency on Zybo

Postby pichldom »

Hello Eli,
thank you for the answer. 70MHz is written here: http://xillybus.com/doc/microblaze-fpga-core-api, but maybe I just misunderstood what it is about (I just tried to Google it and this was one of the first links I got).

Dominika
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Re: Default bus_clk frequency on Zybo

Postby support »

Hi,

The page on the link you gave relates to Xillybus on Microblaze (a rather outdated platform), and it's indeed 70 MHz there. But it has nothing to do with Zynq platforms, Zybo included.

Regards,
Eli
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