Hello,
It's not clear where the 70 MHz figure came from. Anyhow, the bus_clk is another name for the clock called clk_fpga_1 by Vivado. From the timing report of xillinux-eval-zybo-1.3c's demo bundle's implementation on Vivado, we have (the file is xillydemo_timing_summary_routed.rpt)
- Code: Select all
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| Clock Summary
| -------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk_fpga_1 {0.000 5.000} 10.000 100.000
gclk {0.000 4.000} 8.000 125.000
audio_mclk_OBUF {0.000 41.667} 83.333 12.000
clk_fb {0.000 20.000} 40.000 25.000
vga_clk_ins/clk_fb {0.000 20.000} 40.000 25.000
vga_clk_ins/clkout0 {0.000 1.538} 3.077 325.000
vga_clk_ins/clkout1 {0.000 7.692} 15.385 65.000
vga_clk_ins/clkout2 {0.000 7.692} 15.385 65.000
So the answer is 100 MHz.
Regards,
Eli