Error Opt 31-67 in Vivado 2015.4

Questions and discussions about the Xillybus IP core and drivers

Error Opt 31-67 in Vivado 2015.4

Postby knparikh »

Hello,

I've seen a couple of topics regarding this issue before but haven't seen many been resolved. I've been trying to work with Xillybus to implement some simple algorithms on the Zedboard. I successfully got the simple trig function to work (the one hosted on the Xillybus tutorial) and ran into the Opt 31-67 problem, but somehow managed to clear it and get a successful bitstream generation. I've now moved to my own project of a simple matrix multiplier. HLS runs fine, but Vivado is again having issues with generating a bitstream and fails in implementation. I've gotten bitstream generation to succeed with 2013 and 2014 versions of Vivado fairly consistently, but 2015 seems to have some issues. I removed the debug lines in the xillydemo.v as the Xillybus tutorial said, but am now getting these errors:

Image

Thanks for your help!
knparikh
 
Posts: 2
Joined:

Re: Error Opt 31-67 in Vivado 2015.4

Postby support »

Hello,

I'll start with reminding you (and others) of the major disclaimer on the HLS tutorial: http://xillybus.com/tutorials/vivado-hls-c-fpga-howto-1

The HLS flow is quite shaky as of now (March 2016), and it's definitely not supported.

That said, it seems like the error you have there can be eliminated by removing the instantiation of fifo_8.

Regards,
Eli
support
 
Posts: 802
Joined:

Re: Error Opt 31-67 in Vivado 2015.4

Postby knparikh »

Eli,

Thank you for your reply. I was aware of the disclaimer, but decided to push ahead since it worked with all 2014 versions and actually got their straight tutorial to work with the 2015.4 version I'm using. Is there any indication there will ever be an updated tutorial for a Vivado HLS/Vivado workflow? I don't totally understand the note as to why in part 1 of the tutorial, especially when they mention that it's ISE which has a problem with floating point math.

I went ahead and removed the fifo_8 logic you referred to and the bitstream generated, though is currently untested... can't wait to debug it. I'll put my modification here in case anyone stumbles on this thread in the future. Again, thanks for your help, Eli.

Code: Select all
  //fifo_8x2048 fifo_8
     //(
      //.clk(bus_clk),
      //.srst(!user_r_read_8_open),
      //.din(debug_out_din),
      //.wr_en(debug_out_write),
      //.rd_en(user_r_read_8_rden),
      //.dout(user_r_read_8_data),
      //.full(debug_out_full),
      //.empty(user_r_read_8_empty)
      //);

   //assign  user_r_read_8_eof = 0;
   //assign  user_w_write_8_full = 1; // Not used, hence always full
knparikh
 
Posts: 2
Joined:

Re: Error Opt 31-67 in Vivado 2015.4

Postby support »

Hi,
knparikh wrote:I don't totally understand the note as to why in part 1 of the tutorial, especially when they mention that it's ISE which has a problem with floating point math.

The problem is that when certain floating-point operations are used in the C code, Vivado HLS diverts from plain Verilog sources, and injects Tcl sources instead, which are seemingly IP core blocks. So the whole model of adopting HLS' Verilog sources breaks.

So people tried the example, all was fine, and then went for their actual application, just to find out it couldn't be implemented the same way. Hence the disclaimer.

As for an updated tutorial, that is planned, but not in the near future. At least 6-12 months from now.

Regards,
Eli
support
 
Posts: 802
Joined:


Return to Xillybus

cron