Is xillybus fifo interface interchangable with axi-stream?

Questions and discussions about the Xillybus IP core and drivers

Is xillybus fifo interface interchangable with axi-stream?

Postby Guest »

Hi,I want to perform some image processing functions with the help of xillybus ip-core.I am using HLS video libraryhttp://www.wiki.xilinx.com/HLS+Video+Library.I have to use a function like hls::AXIvideo2Mat which inputs an axi-stream input and outputs a MAT data structure that can then be used in a function like hls::harriscorners to find corners and sent back with a function like hls::Mat2AXIvideo through an axi stream output.
Now,long story short.I want to know if this is possible with the fifo interface of xillybus.I read somewhere about axi-stream fifos.Are xillybus fifos axi stream fifos? and can they be used in the same way?Is there any pragma statement that I should use?
My knowledge of vivado HLS is limited.Please, help me by giving some pointers related to this.
Here, is an image of the code which I want to implement with xillybus fifo interface.
http://postimg.org/image/mseivt513
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Re: Is xillybus fifo interface interchangable with axi-strea

Postby support »

Hello,

Xillybus interacts with logic with plain, standard FIFOs. If you refer to AXI Stream FIFOs as in this document,

http://www.xilinx.com/support/documenta ... o-mm-s.pdf

then it's a completely different matter. These AXI FIFOs deal with packets, while standard FIFOs work with a stream of data, with no division into packets.

You may bridge between the two worlds for a specific application by adding glue logic, but that requires some FPGA skills -- not clear if you're into that.

A similar question was asked here, by the way:

viewtopic.php?f=4&t=259

Regards,
Eli
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Re: Is xillybus fifo interface interchangable with axi-strea

Postby Guest »

Hi eli, thanks for the reply.

From your response and the link you provided,what I understand is that the flow of my application would be something like this. input raw stream from fifo--->glue logic for converting to axi stream ---> ip-core that performs operations on axi-stream ---> glue logic for conversion from axi-stream to raw stream --->output raw stream from fifo.
Am I right?

Now, I do know some vhdl/verilog and have done some fpga prototyping but not so good with the Xilinx vivado toolchain.If it is some simple glue logic,could you give me some pointers on how should I implement it and which files i'll need to modify in the HLS-coprocessing demo.I have tried searching for how to convert a raw stream to an axi-stream but couldn't find anything useful.I'd be grateful if you can identify some resource that can guide me towards doing this.

Thanks again.

PS.My data stream is a long stream of bytes that represent image pixels.The host program on linux does the counting of when the complete packet(frame) has been received or sent.
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Re: Is xillybus fifo interface interchangable with axi-strea

Postby support »

Hello,

Unfortunately, I don't have any magical recipe for your case. It's down to understanding the data signals going to and from the HLS logic in your specific case, and of course understanding how a standard FIFO works. And then write the logic that interfaces between the two.

There is no standard solution for this, partly because of the AXI "last" signal which chops the stream into packets (not your case) and partly because of other signals, which may or may not be used (e.g. "keep" signals and other out-of-band signals).

Regards,
Eli
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