I have some questions about setup of your IP core with the ACP port on the Zynq.
1. Is it always recommended to use the ACP port for xillybus if possible? My understanding is that depending on the application and transfer sizes of data chunks is that the HP ports may be a better fit in some cases. My application is streaming data in and out of the processor on asynchronous streams. Total BW over all streams is roughly 100MB/s.
2. Is it required/recommended to check the box in the Vivado ps7 IP box to tie the AxUSER pins high for cache coherent transfers? Does the IP core handle setting the others signals needed or is any custom glue logic required? (dma-coherent is set in device tree). There has been discussion on some of the Xilinx forums relative to what this check box really does and we are scratching our heads at a few memory issues we don't see on X86 platforms with xillybus. Just wanted to check.
https://forums.xilinx.com/t5/Embedded-L ... d-p/595844
3. We have 1GB of DDR memory for the PS on our HW. The address table in Vivado defaults to showing 4 regions and a 512MBs for low DDR. Since we have the ACP port hooked directly to the core without any AXI IP between I believe that the settings in the address table for ACP don't really matter since there is no crossbar doing address translation. Is this correct? If not do you have guidance on what to use in the address table?
3. Is the interrupt input to the PS7 rising edge triggered or level? Vivado is coming up with level sensitive, but I see in your devicetree example you have it marked as rising edge. Can you clarify? Again I "think" that Vivado can come up with what it wants here, but all that really matters for Linux is the devicetree being correct?
4. I guess this is not an ACP port question, but while I am at it I will ask about the latest patch I saw you committed to the Kernel in February. It looks like there is not a reason to run out and patch our kernel, but is there any expected impact for this fix on the Zynq/arm architecture. We are running a 4.1 Kernel from the Yocto Project at the moment.
Thanks for any information you can provide.
Kevin