Hello,
Please refer to section 4.3.3 in the "Getting started with the FPGA demo bundle for Xilinx" guide:
http://xillybus.com/downloads/doc/xilly ... xilinx.pdfYou may generate Xilinx' PCIe block under ISE 13.1, and use the Verilog files in the project in any later ISE version. There's no problem having two versions of ISE on the same computer (or you could even run ISE 13.1 on another computer, since it's a one-off task).
Regards,
Eli