Xillybus core customization for fft spectrometer application

Questions and discussions about the Xillybus IP core and drivers

Xillybus core customization for fft spectrometer application

Postby mugundhan »

Dear Eli,

I'm interested in using Xillybus for a FFT spectropolarimeter application (at our institute's radio observatory). I'll be using a ML505 board which has a single lane PCIe, which I'll be connecting to the PCIe via a PCIe extender Cable. On the front-end is a AD9286 and AD9284 ADCs to stream digitized data from the antennas. I have a 3 channel streaming 16384 point real FFT running in the FPGA (out of which I'll take only the positive half spectrum), from which I get the spectrum of the 3 antennas, which I correlate to obtain the polarized spectrum. I'd be getting 4 spectrum products at intervals of typically 10 ms. I'd be writing 8192 points into 4 FIFOs every 10 ms (this value may vary from 1ms to ~100ms). For this purpose I customized my core as follows in the IP Core factory:
xillybus_read_32 32 bits 195 MB/s No Asynchronous, 4 x 16 kB = 64 kB Data acquisition / playback
xillybus_write_32 32 bits 180 MB/s No Asynchronous, 2 x 16 kB = 32 kB DMA acceleration: 4 segments x 512 bytes Data acquisition / playback
xillybus_read_8 8 bits 1 MB/s Yes General purpose
xillybus_write_8 8 bits 1 MB/s Yes General purpose
xillybus_mem_8 8 bits 102.400 kB/s Yes Address/data interface (5 address bits)
(host to FPGA) 8 bits 102.400 kB/s Yes Address/data interface (5 address bits)

This generates 2 warnings:
xillybus_read_32: This stream can generate about 12400 interrupts per second to the host, which may degrade its performance. An interrupt is sent every time a DMA buffer is filled or emptied. It's therefore recommended to make each DMA buffer larger.
xillybus_write_32: This stream can generate about 11500 interrupts per second to the host, which may degrade its performance. An interrupt is sent every time a DMA buffer is filled or emptied. It's therefore recommended to make each DMA buffer larger.

Is this configuration ok for my application ? Is there a technique to bypass the warnings ? Is there a more optimum setting?
mugundhan
 
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Re: Xillybus core customization for fft spectrometer applica

Postby support »

Hello,

You mention writing into 4 FIFOs, but I can see only one significant data stream from the FPGA to the host. So I assume you sorted this out somehow, by multiplexing the data on your own.

As for the warnings, they indicate that you're going to have a CPU load due to the interrupts. The figures mentioned are probably OK, but not optimal.

What's unclear is why you turned off the Autoset option. The automatic settings would probably be better than what you set there, and the warnings would go away.

In particular, I should mention that there is no required connection between the buffer sizes and the data you want to transport: Xillybus supplies a continuous stream transport, so even if the DMA buffer are considerably larger that the chunks of data transported, it's transparent to the user. You won't get an extra latency: See

http://xillybus.com/doc/xillybus-latency

Regards,
Eli
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Re: Xillybus core customization for fft spectrometer applica

Postby Guest »

Hello,

I'd actually like to have data streaming from four FIFOs. While customizing the core, In the edit option of xillybus_read_32, I gave the number of buffers as 4 and the depths of buffers as 16384. I thought this means that the core will take inputs from 4 FIFOs. Kindly correct me if I'm wrong ! If I'm wrong, how can I customize my core to add multiple FIFOs (while creating them in ip core factory)?

Thanks,

Mugundhan
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Re: Xillybus core customization for fft spectrometer applica

Postby support »

Hello,

If you want four streams of data, you may add four streams of your own to the design in the IP Core Factory, so you have one FIFO connected to each. And then, possibly delete xillybus_read_32, as you probably won't need it.

So it could be like xillybus_adc1, xillybus_adc2, xillybus_adc3 and xillybus_adc4, each set with your desired parameters of bandwidth etc. Keep the autoset on.

That will create you a core with streams, each interfacing with a different FIFO.

Regards,
Eli
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Re: Xillybus core customization for fft spectrometer applica

Postby mugundhan »

Hello,

Thank you so much for the clarification.

I'll try that and get back to you in case of any confusion :)

Thanks,

Mugundhan
mugundhan
 
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Re: Xillybus core customization for fft spectrometer applica

Postby Guest »

Hello,

I have downloaded an ip core with 4 FIFO stream settings (I had 4 devices configured to upstream and one warning it gave me was that the stream rate is ~ >700 MB, but ignore if you're not going to stream continously). So, after this, I installed a version of xilinx ise 13.1, where I opened a project, generated PCIe 1.14 end point-block and added it along with the two verilog files and this sits well in the heirarchy. How do I proceed after this to generate the xillybus core ? The standard xilinx flow for generating custom ip ? or I can stop at the above step and copy this to my main project folder (this is in ISE 14.7)?

Thank you,

Mugundhan
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Re: Xillybus core customization for fft spectrometer applica

Postby support »

Hello,

You should first start with setting up the demo bundle as is. In your case, it includes taking Verilog sources from ISE 13.1 into an ISE 14.7, but it's warmly recommended to have this up and running on a PC first, and go through the simple "Hello World" test, as suggested in the Getting Started Guide.

Once you're passed that, please follow the instructions in the Readme file which is part of what you downloaded from the IP Core Factory. That is, replacing some files and editing the sources so the new IP core is instantiated and hooked up properly.

Regards,
Eli
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Re: Xillybus core customization for fft spectrometer applica

Postby mugundhan »

Hello,

Ok, I'll try that first.

Thank you,

Mugundhan
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Re: Xillybus core customization for fft spectrometer applica

Postby mugundhan »

Hello,

When I try to implement this design in 14.7 after creating the pcie cores in 13.1, I get the following errors during the implementation:

ERROR:ConstraintSystem:58 - Constraint <INST
"*/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC =
GTP_DUAL_X0Y2;> [src/virtex5.ucf(3)]: INST
"*/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" does not match any
design objects.
ERROR:ConstraintSystem:59 - Constraint <INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst" LOC = RAMB36_X3Y9;> [src/virtex5.ucf(17)]: INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst
" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y13;> [src/virtex5.ucf(18)]: INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2
_inst" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X3Y12;> [src/virtex5.ucf(19)]: INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2
_inst" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y11;> [src/virtex5.ucf(20)]: INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2
_inst" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:59 - Constraint <INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X3Y10;> [src/virtex5.ucf(21)]: INST
"ep/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2
_inst" not found. Please verify that:
1. The specified design element actually exists in the original design.
2. The specified object is spelled correctly in the constraint source file.
ERROR:ConstraintSystem:58 - Constraint <NET
"*/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out" TNM_NET = "MGTCLK"
;> [src/virtex5.ucf(26)]: NET
"*/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out" does not match any
design objects.
ERROR:NgdBuild:604 - logical block 'xillybus_ins/pcie_v5' with type 'pcie_v5'
could not be resolved. A pin name misspelling can cause this, a missing edif
or ngc file, case mismatch between the block name and the edif or ngc file
name, or the misspelling of a type name. Symbol 'pcie_v5' is not supported in
target 'virtex5'.
ERROR:NgdBuild:604 - logical block 'xillybus_ins/xillybus_core_ins' with type
'xillybus_core' could not be resolved. A pin name misspelling can cause this,
a missing edif or ngc file, case mismatch between the block name and the edif
or ngc file name, or the misspelling of a type name. Symbol 'xillybus_core'
is not supported in target 'virtex5'.

I have matched the GTPs in the ucf to that of Virtex 5 lx110t fpga on XUPV5 board. I have also made changes to the configuration file of the cpld on the board to move the PCIE_PERST_B to the fpga.

Kindly advice

Thanks
mugundhan
 
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Re: Xillybus core customization for fft spectrometer applica

Postby mugundhan »

Sorry for the disturbance Eli, my bad.

Instead of importing the src verilog files, i was importing the files from the example design. I was able to implement the demo design for lx110t successfully in 13.1. I'll see if it works if I import the files to 14.7 and see how it goes and then I'll try to run the demo connecting my board to PC.

Will keep you posted !

Thanks for the help !

Mugundhan
mugundhan
 
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