Hello Eli,
I was able to implement successfully the xillydemo on my xupv5lx110t board. I was able to do loop back tests on my host computer. Just correct me if I'm wrong,
when we do the cat > /dev/xillybus_write_8 and cat /dev/xillybus_read_8 functions in the terminal, the 8 bit fifo's srst is deasserted and when data is typed into the pipe of write_8, the core (probably) holds the wr_en of the FIFO high for (length of data)/8 clocks and the data is written to the fifo. The rd_en is high since we opened the read pipe, thus enabling the loopback, after all the data is read, the empty is high and the core waits for this to go low again for taking data from the fifo.
Is this description right?
the use of eof is not still clear to me. but I'll try reading more on it from the fpga designer's guide
Thank you,