Inclusion in a custom project
Posted:
Hello!
First off, thank you for providing the core and allowing us to try it on our projects.
I would like to integrate Xillybus into a Vivado block design. I have a few questions about how I'm doing it and perhaps to see if you have any better ideas about integration.
I have read through the demo bundle file and have successfully generated and tested the bitfile with Vivado on my Xilinx VC707 board. I am stuck on chapter 4.2 Inclusion in a custom project. I did what it said and modified the xillydemo-vivado.tcl script to create a fresh project. I also changed add_files to import_files and other things so that the new project doesn't look back at the xillybus directory (core, vivado-essentials) and just looks internally for the files. Vivado is happy and generated a good bitfile at this point.
I thought I should then use the "Package IP" feature and convert the xillybus demo into a standalone IP.
I clicked through and tried to answer the questions as best as I could and generated an IP. Now that I have it instantiated in the block design, I don't know how to connect the xillybus ports to VC707's PCIe pins. I didn't have an interface for the "create interface port" and I tried to create individual pins for it but then I couldn't find the netlist. At this point, I feel like I'm doing it wrong and thought I should see if you have any insight on what to do.
I don't have a preference as to the method of including xillybus integrated with block design just as long as I could get a microblaze, some AXI cores, and some custom vhdl logic all working together.
Any advice would be so appreciated.
Thank you,
Dave
First off, thank you for providing the core and allowing us to try it on our projects.
I would like to integrate Xillybus into a Vivado block design. I have a few questions about how I'm doing it and perhaps to see if you have any better ideas about integration.
I have read through the demo bundle file and have successfully generated and tested the bitfile with Vivado on my Xilinx VC707 board. I am stuck on chapter 4.2 Inclusion in a custom project. I did what it said and modified the xillydemo-vivado.tcl script to create a fresh project. I also changed add_files to import_files and other things so that the new project doesn't look back at the xillybus directory (core, vivado-essentials) and just looks internally for the files. Vivado is happy and generated a good bitfile at this point.
I thought I should then use the "Package IP" feature and convert the xillybus demo into a standalone IP.
I clicked through and tried to answer the questions as best as I could and generated an IP. Now that I have it instantiated in the block design, I don't know how to connect the xillybus ports to VC707's PCIe pins. I didn't have an interface for the "create interface port" and I tried to create individual pins for it but then I couldn't find the netlist. At this point, I feel like I'm doing it wrong and thought I should see if you have any insight on what to do.
I don't have a preference as to the method of including xillybus integrated with block design just as long as I could get a microblaze, some AXI cores, and some custom vhdl logic all working together.
Any advice would be so appreciated.
Thank you,
Dave