Inclusion in a custom project

Questions and discussions about the Xillybus IP core and drivers

Inclusion in a custom project

Postby Guest »

Hello!

First off, thank you for providing the core and allowing us to try it on our projects.

I would like to integrate Xillybus into a Vivado block design. I have a few questions about how I'm doing it and perhaps to see if you have any better ideas about integration.

I have read through the demo bundle file and have successfully generated and tested the bitfile with Vivado on my Xilinx VC707 board. I am stuck on chapter 4.2 Inclusion in a custom project. I did what it said and modified the xillydemo-vivado.tcl script to create a fresh project. I also changed add_files to import_files and other things so that the new project doesn't look back at the xillybus directory (core, vivado-essentials) and just looks internally for the files. Vivado is happy and generated a good bitfile at this point.

I thought I should then use the "Package IP" feature and convert the xillybus demo into a standalone IP.

I clicked through and tried to answer the questions as best as I could and generated an IP. Now that I have it instantiated in the block design, I don't know how to connect the xillybus ports to VC707's PCIe pins. I didn't have an interface for the "create interface port" and I tried to create individual pins for it but then I couldn't find the netlist. At this point, I feel like I'm doing it wrong and thought I should see if you have any insight on what to do.

I don't have a preference as to the method of including xillybus integrated with block design just as long as I could get a microblaze, some AXI cores, and some custom vhdl logic all working together.

Any advice would be so appreciated.

Thank you,
Dave
Guest
 

Re: Inclusion in a custom project

Postby support »

Hello,

I'm not sure if this is the right place to ask this question. It seems like it's about IP packaging, and not so much about Xillybus itself.

Anyhow, you didn't mention what part you decided to package as an IP, but it seems like you picked the xillybus module for that. In your case, I would go for the entire design: Turn xillydemo (the toplevel module) into the IP.

After all, the Xillybus demo bundle is just a design with some HDL, constraints, a netlist file and a PCIe block. If you package that, all toplevel ports should turn into the IP's port. So that should include the PCIe pins, clock, reset and the LEDs.

If you want the packaged IP to interact with the other blocks, you can add other toplevel ports, which turn into the new IP's interface ports.

Frankly speaking, I don't know how well it will work. Never tried IP packaging for real myself. The thing to look out for is if attributes or constraints are lost on the way. This is the typical caveat of those magic tools.

For example, you mentioned that the netlist couldn't be found. Maybe it's because the search part for netlists is a property of the xillydemo project, so that wasn't propagated into the packaged IP (which kind-of makes sense). So all you need to do is to make sure that your xillybus_core.ngc/.edf file is in the "macro search path" (or something like that) in the new main project.

Regards,
Eli
support
 
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Re: Inclusion in a custom project

Postby Guest »

Hey Eli,

Sorry if it was a little off topic, but thank you for nevertheless responding to it and in such a short time as well. Given that you've never really tried the IP Packager, I didn't want to go down that avenue.

Instead, what I did was to start with the baseline Xillydemo, created a block design, created a wrapper for the block design, and then instantiated the wrapper in xillydemo.vhd. It worked perfectly. I was worried about connecting to external pins for the block design, but Vivado already had the netlist for the board so everything synthesized and implemented happily.

Dave
Guest
 


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